TDA10023HT

www.DataSheet4U.com TDA10023HT Single chip DVB-C/MCNS channel receiver Rev. 01 — 12 April 2005 Product data sheet 1. General description The TDA10023HT is a single chip DVB-C/MCNS channel receiver for 4, 16, 32, 64, 128 and 256-QAM modulated signals. The device interfaces directly to the IF signal, which is sampled by a 10-bit A/D converter. The TDA10023HT performs the clock and the carrier recovery functions. The digital loop filters for both clock and carrier recovery are programmable in order to optimize their characteristics according to the current application. After baseband conversion, equalization filters are used for echo cancellation in cable applications. These filters are configured as T-spaced transversal equalizer or DFE equalizer, so that the system performance can be optimized according to the network characteristics. A proprietary equalization algorithm, independent of carrier offset, is achieved in order to assist carrier recovery. Then a decision directed algorithm takes place, to achieve final equalization convergence. The TDA10023HT chip implements two FEC decoders, one for each standard. In the DVB-C mode the TDA10023HT implements a Forney convolutional de-interleaver of depth 12 blocks and a Reed-Solomon decoder which corrects up to 8 erroneous bytes. The de-interleaver and the Reed-Solomon decoder are automatically synchronized thanks to the frame synchronization algorithm that uses the MPEG2 sync byte. Finally descrambling according to DVB-C standard is ...