Document
STRUCTURE TYPE PRODUCT SERIES FEATURES
Silicon Monolithic Integrated Circuit
Single Channel Series Regulator Driver IC
BD3520FVM
・Non Rush Current on Start up (NRCS) ・N channel MOSFET driver ・Output Voltage : 1.2V (±1%)
○ ABSOLUTE MAXIMUM RATINGS(Ta=25℃)
Parameter
Symbol
Supply Voltage
VCC
Drain Voltage (VIN)
VD
Enable Input Voltage
Ven
Power Dissipation
Pd
Operating Temperature Range
Topr
Storage Temperature Range
Tstg
Maximum Junction Temperature
Tjmax
*1 Operating temperature range should not exceed Tjmax=150℃ *2 Pd derating at 3.5mW/℃ for temperature above Ta=25℃
Limit 7 *1
7
7 437.5 *2 -10~+100 -55~+150
+150
Unit V V V
mW ℃ ℃ ℃
○ RECOMMENDED OPERATING CONDITIONS(Ta=25℃)
PARAMETER
SYMBOL
Supply Voltage
VCC
Drain Voltage(VIN)
VD
Enable Input Voltage
Ven
Capacitor on NRCS Terminal
CNRCS
★ This product is not designed for protection against radioactive rays.
MIN 4.5 1.2 -0.3 0.001
MAX 5.5 5.5 5.5 1
UNIT V V V uF
1/4
REV. A
2/4
○ ELECTRICAL CHARACTERISTICS (Unless otherwise specified,Ta=25℃ VCC=5V VIN=3.3V Ven=3V)
PARAMETER
SYMBOL MIN
LIMIT TYP
Bias Current
ICC - 0.85
Shut Down Mode Current
IST - 0
Output Voltage 1
Vo1 1.188 1.200
MAX 1.7 10 1.212
Output Voltage 2
Vo2 1.176 1.200 1.224
Line Regulation Load Regulation [Enable] High Level Enable Input Voltage Low Level Enable Input Voltage Enable pin Input Current [Source Voltage] VS Input Bias Current VS Standby Current [Output MOSFET Driver] MOSFET Driver Source Current MOSFET Driver Sink Current [UVLO] VCC UVLO VCC UVLO Hysterisis VD UVLO [Drain Voltage Sensing] VD Input bias Current [NRCS/SCP] NRCS Charge Current SCP Charge Current SCP Discharge Current SCP Threshold Voltage Short Detect Voltage NRCS Stand-by Voltage
(※) Design Guarantee
Reg.l Reg.L
-
0.1 0.5 0.5 10
Enhi
2
- Vcc
Enlow Ien
-0.3 -
7
0.8 10
ISBIAS
-
1.2 2.4
ISSTB
150
-
-
IGSO
2
3
4
IGSI
2
3
4
VccUVLO 4.20 4.35 4.50
Vcchys
100
160
220
VDUVLO Vo×0.6 Vo×0.7 Vo×0.8
Ivd 10 16 22
Inrcs Iscpch IscpDi Vscp Voscp VSTB
14 14 0.3 1.2 Vo×0.3 -
20 20 1.3 Vo×0.35 -
26 26 1.4 Vo×0.4 50
UNIT
CONDITIONS
mA uA Ven=0V V Io=50mA
Vcc=4.5V to 5.5V , V Ta=-10℃ to 100℃(※) %/V VCC=4.5V to 5.5V mV Io=0 to 3A
V
V uA Ven=3V
mA mA VS=1V Ven=0V
mA VFB=1.1V,VGATE=2.5V
mA VFB=1.3V,VGATE=2.5V
V Vcc:Sweep up mV Vcc:Sweep down V VD:Sweep up
uA
uA VNRCS=0.5V uA VNRCS=0.5V mA VNRCS=0.5V V V mV
REV. A
○ PHYSICAL DIMENSIONS
D35 20
1PIN MARK Lot No.
3/4
(UNIT:mm) MSOP8
○ BLOCK DIAGRAM
VCC
C1
VCC 4
EN 3
Enable
Reference Block
Thermal Protection
+ -
0.65V
UVLO2 UVLO1
VD UVLO LATCH
NRCS 0.65V
TSD SCP UVLO1 UVLO2 EN
UVLO1 VREF EN
TSD
0.65V
+
SCP
SCP
○ Pin number Pin name
VD 8
VIN C2
G 7
VS 6
VFB 5
VO C4
PIN PIN Name No.
1 NRCS 2 GND 3 EN 4 VCC 5 VFB 6 VS 7G 8 VD
NRCS
NRCS
1 NRCS
C3
2 GND
REV. A
4/4
○NOTES FOR USE
(1) Absolute maximum range
Although the quality of this product is rigorously controlled, and circuit operation is guaranteed within the operation ambient
temperature range, the device may be destroyed when applied voltage or operating temperature exceeds its absolute maximum
rating. Because the failure mode (such as short mode or open mode) cannot be identified in this instance, it is important to take
physical safety measures such as fusing if a specific mode in excess of absolute rating limits is considered for implementation.
(2) Ground potential
Make sure the potential for the GND pin is always kept lower than the potentials of all other pins, regardless of the operating
mode, including transient conditions.
(3) Thermal Design
Provide sufficient margin in the thermal design to account for the allowable power dissipation (Pd) expected in actual use.
(4) Using in the strong electromagnetic field
Use in strong electromagnetic fields may cause malfunctions.
(5) ASO
Be sure that the output transistor for this IC does not exceed the absolute maximum ratings or ASO value.
(6) Thermal Protection Circuit
A thermal shutdown circuit (T.S.D) is built into the IC to prevent damage due to overheating. Therefore, all the outputs are turned
off when the T.S.D circuit is activated. (This IC latches output to off mode when the temperature recedes to the specified level.
To release latch mode, EN or UVLO is re-operated.) However, the T.S.D circuit is used only for extreme conditions, and the
regulator circuit should still be designed for the IC not to exceed Tj(max)=150℃.
(7) GND pattern
When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is
recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change stemming
from the wiring resistance and high current does not cause any voltage change in the small-signal GND. In the same way, care
must be taken to avoid wiring pattern fluctuations in any connected external component GND.
(8) Output Capacitor (C4)
Mount an output capacitor betwe.