Document
ADC1410S series
Rev. 03 — 12 April 2010
www.DataSheet4U.com
Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs
Preliminary data sheet
1. General description
The ADC1410S is a single-channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1410S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, because of a separate digital output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1410S is ideal for use in communications, imaging and medical applications.
2. Features and benefits
SNR, 72 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps 14-bit pipelined ADC core Clock input divider by 2 for less jitter contribution Single 3 V supply Flexible input voltage range: 1 V to 2 V (peak-to-peak). CMOS or LVDS DDR digital outputs Pin compatible with the ADC1210S series and the ADC1010S series HVQFN40 package Input bandwidth, 600 MHz Power dissipation, 430 mW at 80 Msps Serial Peripheral Interface (SPI) Duty cycle stabilizer
Fast OuT of Range (OTR) detection INL ±1.5 LSB, DNL ±0.5 LSB Offset binary, two’s complement, gray code Power-down and Sleep modes
3. Applications
Wireless and wired broadband communications Spectral analysis Ultrasound equipment Portable instrumentation Imaging systems Software define radio
NXP Semiconductors
ADC1410S series www.DataSheet4U.com
ADC1410S series; CMOS or LVDS DDR digital output
4. Ordering information
Table 1. Ordering information fs (Msps) Package Name ADC1410S125HN/C1 125 ADC1410S105HN/C1 105 ADC1410S080HN/C1 80 ADC1410S065HN/C1 65 Description Version SOT618-6 SOT618-6 SOT618-6 SOT618-6 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm Type number
5. Block diagram
SDIO/ODS SCLK/DFS CS
ADC1410S
ERROR CORRECTION AND DIGITAL PROCESSING SPI INTERFACE
OTR CMOS: D13 to D0 or LVDS/DDR: D13_M to D0_M D13_P to D0_P CMOS: DAV or LVDS/DDR: DAVP DAVM
INP T/H INPUT STAGE INM ADC CORE 14-BIT PIPELINED OUTPUT DRIVE.