ICS8633-01

Integrated Circuit Systems, Inc. ICS8633-01 www.DataSheet4U.com 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER GENERAL DESCRIPTION The ICS8633-01 is a high performance 1-to-3 Differential-to-3.3V LVPECL Zero Delay Buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8633-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most standard differential input levels. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications. FEATURES Three differential 3.3V LVPECL outputs Selectable differential clock inputs CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Output frequency range: 31.25MHz to 700MHz Input frequency range: 31.25MHz to 700MHz VCO range: 250MHz to 700MHz External feedback for “zero delay” clock regeneration Cycle-to-cycle jitter: 25ps (maximum) Output skew: 25ps (maximum) PLL reference zero delay: 50ps ± 100ps 3.3V operating supply 0°C to 70°C ambient operating temperature Industrial temperature information available upon request Available in both standard and lead-free RoHs-compliant packages IC S BLOCK DIAGRAM PLL_SEL ÷4, ÷8 0 1 1 Q2 nQ2 Q0 nQ0 0 Q1 nQ1 PIN ASSIGNMENT PLL_SEL VCC SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR VCC...