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M58LR256GU, M58LR256GL M58LR128GU, M58LR128GL
128 and 256Mbit (x16, Mux I/O, Multiple Bank, Multi-Level, Burst) 1.8V supply Flash memories
Feature summary
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Supply voltage – VDD = 1.7V to 2.0V for program, erase and read – VDDQ = 1.7V to 2.0V for I/O Buffers – VPP = 9V for fast program Multiplexed address/data Synchronous / Asynchronous Read – Synchronous Burst Read mode: 66MHz – Random Access: 85ns (M58LR128GU/L) 90ns (M58LR256GU/L) Synchronous Burst Read Suspend Programming time – 10µs typical Word program time using Buffer Enhanced Factory Program command Memory organization – Multiple Bank Memory Array: 16 Mbit (M58LR256GU/L) or 8 Mbit (M58LR128GU/L) Banks – Parameter Blocks (Top or Bottom location) Dual operations – program/erase in one Bank while read in others – No delay between read and write operations Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – WP for Block Lock-Down – Absolute Write Protection with VPP = VSS Security – 64 bit unique device number – 2112 bit user programmable OTP Cells Common Flash Interface (CFI)
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FBGA
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VFBGA44 (ZC) 8 x 10mm VFBGA44 (ZB) 7.7 x 9mm
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100,000 program/erase cycles per block Electronic signature – Manufacturer Code: 20h – Top Device Codes: M58LR256GU: 882Ch M58LR128GU: 882Eh – Bottom Device Codes M58LR256GL: 882Dh M58LR128GL: 882Fh ECOPACK® packages available
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June 2006
Rev 1
1/114
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Contents
M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 Address Inputs (ADQ0-ADQ15 and A16-Amax) . . . . . . . . . . . . . . . . . . . 15 Data Input/Output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VDDQ supply .