K4X51323PC-7E

Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM www.DataSheet4U.com 16M x32 Mobile-DDR SDRAM 1 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Document Title 16M x32 Mobile-DDR SDRAM Mobile-DDR SDRAM Revision History Revision No. History 0.0 0.1 0.2 - First version for target specification - Insertion of PKG dimension of 90FBGA JEDEC Standard type. - Preliminary Datasheet - Insertion DC Current value. - Changing Frequency from DDR333/DDR266 to DDR266/DDR222. - Updating DC current value. - Changing expression of PKG dimension. - Changing format with JEDEC standard type. - Insertion of Normal power bin. - Changing IDD3P/3PS - Changing IDD6 limit. - Define maximum burst refresh cycle. - Add a note related with Vdd & Vddq. - Add a note related with IDD8. Draft Date October 27. 2004 Remark Target Target December 13. 2004 December 20. 2004 Preliminary www.DataSheet4U.com 0.3 February 15. 2005 Preliminary 0.4 0.5 February 18. 2005 Preliminary September 07. 2005 Preliminary 0.6 October 18. 2005 Preliminary 2 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G 16M x32 Mobile-DDR SDRAM FEATURES Mobile-DDR SDRAM 1.8V power supply, 1.8V I/O power Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Four banks operation 1 /CS 1 CKE Differential clock inputs(CK and CK) MRS cycle with address key programs - CAS Latency ( 2, 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential...