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K4X1G163PC-FG Dataheets PDF



Part Number K4X1G163PC-FG
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description Mobile DDR SDRAM
Datasheet K4X1G163PC-FG DatasheetK4X1G163PC-FG Datasheet (PDF)

K4X1G163PC - L(F)E/G 64Mx16 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) • EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( F.

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K4X1G163PC - L(F)E/G 64Mx16 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) • EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 ) • Internal Temperature Compensated Self Refresh • All inputs except data & DM are sampled at the positive going edge of the system clock(CK). www.DataSheet4U.com • Data I/O transactions on both edges of data strobe, DM for masking. • Edge aligned data output, center aligned data input. • No DLL; CK to DQS is not synchronized. • LMD, UMD for write masking only. • Auto refresh duty cycle - 7.8us for -25 to 85 °C Mobile DDR SDRAM 2. Operating Frequency DDR333 Speed @CL2 Speed @CL3 NOTE: 1) CAS Latency 1) 1) DDR266 83Mhz 133Mhz 83Mhz 166Mhz 3. Address configuration Organization 64Mx16 - DM is internally loaded to match DQ and DQS identically. Bank Address BA0,BA1 Row Address A0 - A13 Column Address A0 - A9 4. Ordering Information Part No. K4X1G163PC-L(F)E/GC6 K4X1G163PC-L(F)E/GC3 Max Freq. 166MHz(CL=3),83MHz(CL=2) 133MHz(CL=3),83MHz(CL=2) Interface LVCMOS Package 60FBGA Pb (Pb Free) - L(F)E : 60FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C) - L(F)G : 60FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C) - C6/C3 : 166MHz(CL=3) / 133MHz(CL=3) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. -4- November 2007 K4X1G163PC - L(F)E/G 5. FUNCTIONAL BLOCK DIAGRAM Mobile DDR SDRAM 16 LWE LDM I/O Control CK, CK Data Input Register Serial to parallel Bank Select 32 16Mx16 Output Buffer 2-bit prefetch www.DataSheet4U.com Sense AMP Refresh Counter Row Buffer Row Decoder 16Mx16 16Mx16 16Mx16 32 16 X16 DQi Address Register CK, CK ADD Column Decoder LCBR LRAS Col. Buffer Latency & Burst Length Strobe Gen. Data Strobe LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDM Timing Register DM Input Register CK, CK CKE CS RAS CAS WE DM -5- November 2007 K4X1G163PC - L(F)E/G 6. Package Dimension and Pin Configuration < Bottom View*1 > E1 9 A e B C D D1 E D F G A B C D E F G H J K E 8 7 6 5 4 3 2 1 1 VSS VDDQ VSSQ VDDQ VSSQ VSS CKE A9 A6 VSS Mobile DDR SDRAM < Top View*2 > 60Ball(6x10) FBGA 2 DQ15 DQ13 DQ11 DQ9 UDQS UDM CK A11 A7 A4 3 VSSQ DQ14 DQ12 DQ10 DQ8 N.C. CK A12 A8 A5 7 VDDQ DQ1 DQ3 DQ5 DQ7 A13 WE CS A10/AP A2 8 DQ0 DQ2 DQ4 DQ6 LDQS LDM CAS BA0 A0 A3 9 VDD VSSQ VDDQ VSSQ VDDQ VDD RAS BA1 A1 VDD www.DataSheet4U.com H J K *2: Top View Ball Name CK, CK CS A A1 b CKE A0 ~ A13 BA0 ~ BA1 RAS CAS WE L(U)DM L(U)DQS DQ0 ~ 15 VDD/VSS Ball Function System Differential Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input Mask Data Strobe Data Input/Output Power Supply/Ground Data Output Power/Ground z *1: Bottom View < Top View*2 > #A1 Ball Origin Indicator K4X1G163PC-XXXX SAMSUNG Week -6- VDDQ/VSSQ [Unit:mm] Symbol A A1 E E1 D D1 e b z Min 0.25 10.9 11.4 0.45 Typ 11.0 6.4 11.5 7.2 0.80 0.50 Max 1.0 11.1 11.6 0.55 0.10 November 2007 K4X1G163PC - L(F)E/G 7. Input/Output Function Description Symbol CK, CK Type Input Description Mobile DDR SDRAM Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK. Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are contrived for low standby power consumption. Chip Select : CS enable.


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