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IDT72V7280 Dataheets PDF



Part Number IDT72V7280
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description (16384 x 72)3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
Datasheet IDT72V7280 DatasheetIDT72V7280 Datasheet (PDF)

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO 512 x 72, 1,024 x 72 2,048 x 72, 4,096 x 72 8,192 x 72, 16,384 x 72 32,768 x 72, 65,536 x 72 www.DataSheet4U.com IDT72V7230, IDT72V7240 IDT72V7250, IDT72V7260 IDT72V7270, IDT72V7280 IDT72V7290, IDT72V72100 FEATURES: • • • • • • • Choose among the following memory organizations: IDT72V7230  512 x 72 IDT72V7240  1,024 x 72 IDT72V7250  2,048 x 72 IDT72V7260  4,096 x 72 IDT72V7270  8,192 x 72 IDT72V7280  16,384 x 72 IDT72V7290  32,768 x 72 .

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3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO 512 x 72, 1,024 x 72 2,048 x 72, 4,096 x 72 8,192 x 72, 16,384 x 72 32,768 x 72, 65,536 x 72 www.DataSheet4U.com IDT72V7230, IDT72V7240 IDT72V7250, IDT72V7260 IDT72V7270, IDT72V7280 IDT72V7290, IDT72V72100 FEATURES: • • • • • • • Choose among the following memory organizations: IDT72V7230  512 x 72 IDT72V7240  1,024 x 72 IDT72V7250  2,048 x 72 IDT72V7260  4,096 x 72 IDT72V7270  8,192 x 72 IDT72V7280  16,384 x 72 IDT72V7290  32,768 x 72 IDT72V72100  65,536 x 72 100 MHz operation (10 ns read/write cycle time) User selectable input and output port bus-sizing - x72 in to x72 out - x72 in to x36 out - x72 in to x18 out - x36 in to x72 out - x18 in to x72 out Big-Endian/Little-Endian user selectable word representation Fixed, low first word latency Zero latency retransmit Auto power down minimizes standby power consumption • • • • • • • • • • • • • • • • Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state Easily expandable in depth and width Independent Read and Write Clocks (permit reading and writing simultaneously) Asynchronous operation of Output Enable, OE Read Chip Select ( RCS ) on Read Side Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA) Features JTAG (Boundary Scan) High-performance submicron CMOS technology Industrial temperature range (–40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x72, x36 or x18) WEN WCLK LD SEN SCLK INPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 WRITE CONTROL LOGIC WRITE POINTER RAM ARRAY 512 x 72 1,024 x 72 2,048 x 72 4,096 x 72 8,192 x 72 16,384 x 72 32,768 x 72 65,536 x 72 FLAG LOGIC READ POINTER BE IP BM IW OW MRS PRS TCK TRST TMS TDO TDI CONTROL LOGIC BUS CONFIGURATION RESET LOGIC JTAG CONTROL (BOUNDARY SCAN) OUTPUT REGISTER READ CONTROL LOGIC RT RM RCLK REN RCS Q0 -Qn (x72, x36 or x18) 4680 drw01 OE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DECEMBER 2003 DSC-4680/9 IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO 512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72 COMMERCIAL TEMPERATURE RANGE DESCRIPTION: The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/ 72V7290/72V72100 are exceptionally deep, high speed, CMOS First-In-FirstOut (FIFO) memories with clocked read and write controls and a flexible BusMatching x72/x36/x18 data flow. These FIFOs offer several key user benefits: • Flexible x72/x36/x18 Bus-Matching on both read and write ports • The period required by the retransmit operation is fixed and short. • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. • High density offerings up to 4 Mbit Bus-Matching Sync FIFOs are particularly appropriate for network, video, www.DataSheet4U.com telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 72-bit, 36-bit or a 18-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and BusMatching (BM) pin during the Master Reset cycle. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input PIN CONFIGURATION A1 BALL PAD CORNER A Q33 Q35 Q34 Q30 Q28 Q16 Q13 Q10 Q61 Q58 Q55 Q43 Q40 Q37 Q25 Q21 Q22 Q47 Q46 Q45 Q27 Q15 Q12 Q9 Q60 Q57 Q54 Q42 Q39 Q36 Q18 Q19 Q20 Q50 Q49 Q48 VCC VCC VCC VCC VCC VCC VCC VCC VCC RT Q6 Q7 Q8 Q53 Q52 Q51 GND GND GND Q65 Q64 Q63 Q68 Q67 Q66 Q71 Q70 Q69 TCK VCC VCC VCC VCC VCC VCC D71 D70 D69 TDI GND D68 D67 D66 D65 D64 D63 D53 D52 D51 TMS VCC VCC VCC VCC VCC VCC GND D50 D49 D48 GND GND GND GND GND GND GND IW D47 D46 D45 D27 D15 D12 D9 D60 D57 D54 D42 D35 D34 D30 D28 D16 D13 D10 D61 D58 D55 D43 D40 D37 D25 D21 D22 D33 D32 D31 D29 D17 D14 D11 D62 D59 D56 D44 D41 D38 D26 D24 D23 B Q32 C Q31 D Q29 VCC GND VCC VCC GND GND GND GND GND GND TRST TDO VCC GND GND GN.


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