W332M64V-XBX

White Electronic Designs 32Mx64 Synchronous DRAM FEATURES High Frequency = 100, 125, 133MHz Package: 219 Plastic Ball Grid Array (PBGA), 25 x 25mm 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 8192 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 32M x 64 Weight: W332M64V-XBX - 2.5 grams typical W332M64V-XBX www.DataSheet4U.com GENERAL DESCRIPTION The 256MByte (2Gb) SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. Each of the chip’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A012 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst acce...