Document
Ordering number : EN*4250C
CMOS LSI
LC78816MB, 78816MC
16-Bit D/A Converter for Use in Digital Audio Products
Preliminaly Overview
The LC78816MB and 78816MC are 16-bit CMOS D/A converters for use in digital audio products. They employ a dynamic level shift conversion technique that combines a resistor string (for the upper 9 bits), PWM (for the middle 3 bits), and level shifting (for the lower 4 bits).
Package Dimensions
unit: mm 3036B-MFP20
[LC78816MB, 78816MC]
Features
• Two’s complement data format • Two D/A converter channels built in (in-phase outputs) • Maximum conversion frequency of 400 kHz (support for 8 times oversampling) • Built-in output op amps • No deglitching circuit required • Si gate CMOS process (low power consumption) • 5 V single-voltage power supply • Low voltage (3.5 V) operation possible
SANYO: DIP20
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter Maximum power supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD max VIN VOUT Topr Tstg Conditions Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –30 to +75 –40 to +125 Unit V V V °C °C
Allowable Operating Ranges
Parameter Power supply voltage Reference voltage high Reference voltage low Operating temperature Symbol VDD VrefH VrefL Topr Conditions Ratings min 3.5 VDD – 0.3 0 –30 typ 5.0 max 5.5 VDD 0.3 +75 Unit V V V °C
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63096HA (OT)/D1694TH(OT)/61893JN No. 4250-1/11
LC78816MB, 78816MC DC Characteristics at Ta = –30 to +75°C, VDD = 3.5 to 5.5 V, VSS = 0 V
Parameter Input high level voltage (1) Input low level voltage (1) Input high level voltage (2) Input low level voltage (2) Symbol VIH VIL VIH VIL Conditions Input pins other than SYSCLK Input pins other than SYSCLK The SYSCLK pin The SYSCLK pin 0.7 VDD 0.3 VDD Ratings min 2.2 0.8 typ max Unit V V V V
AC Characteristics at Ta = –30 to +75°C, VDD = 3.5 to 5.5 V, VSS = 0 V
Parameter Symbol Conditions Ratings min typ max Unit
Clock pulse width Setup time Hold time
tCW tBCW tDS tDH
SYSCLK BCLK LRCK/WCLK DATAL DATAR
25 35 20 20
ns ns ns ns
No. 4250-2/11
LC78816MB, 78816MC Electrical Characteristics (1) at Ta = 25°C, DVDD = AVDD = VrefH = 5.0 V, DGND = AGND = VrefL = 0.0 V
Parameter Resolution Conversion frequency Total harmonic distortion Total harmonic distortion Dynamic range Cross talk Signal to noise ratio Full scale output voltage Power dissipation Output load resistance Symbol RES fs THD1 THD1 DR C·T S/N VFS Pd RL Pins 1 and 20 5 LC78816MB at 1 kHz, 0 dB LC78816MC at 1 kHz, 0 dB At 1 kHz, –60 dB At 1 kHz, 0 dB JIS-A 96 3.0 3.3 35 3.5 60 94 96 –85 Conditions Ratings min typ 16 400 0.05* 0.08 max Unit Bits kHz % % dB dB dB Vp-p mW kΩ
Notes: *: Screened units Test circuit: based on the sample application circuit, with a sampling frequency (fs) of 88.2 kHz.
Electrical Characteristics (2) at Ta = 25°C, DVDD = AVDD = VrefH = 5.0 V, DGND = AGND = VrefL = 0.0 V
Parameter Resolution Conversion frequency Total harmonic distortion Total harmonic distortion Dynamic range Cross talk Signal to noise ratio Full scale output voltage Power dissipation Output load resistance Symbol RES fs THD1 THD1 DR C·T S/N VFS Pd RL Pins 1 and 20 15 LC78816MB at 1 kHz, 0 dB LC78816MC at 1 kHz, 0 dB At 1 kHz, –60 dB At 1 kHz, 0 dB JIS-A 96 2.0 2.3 10 2.5 20 92 94 –85 Conditions Ratings min typ 16 400 0.06* 0.09 max Unit Bits kHz % % dB dB dB Vp-p mW kΩ
Notes: *: Screened units Test circuit: based on the sample application circuit, with a sampling frequency (fs) of 88.2 kHz.
Pin Assignment
No. 4250-3/11
LC78816MB, 78816MC
Block Diagram
Pin Functions
Pin No. 1 2 3 4 5 Pin Name CH1OUT REFH VrefH AVDD LRCK/WCLK Channel 1 output pin (left channel) Reference voltage high level pin Normally connected to AGND through a capacitor. Reference voltage high level input pin Analog system power supply voltage pin LR clock and word clock input pin Used to generate the internal signal that latches the digital audio data (DATAL and DATAR). Digital audio data input pin Data is input from the MSB bit serially. When FSEL is low, channel 1 data is input. When FSEL is high, channel 1 and channel 2 data are input using time division. Digital audio data input pin Data is input from the MSB bit serially. When FSEL is low, channel 2 data is input. When FSEL is high, functions as the interface switching pin. Bit clock input pin This is the clock for reading in digital audio data bit serially. Also functions as the IC’s system clock when SYSCLK is fixed low or high. System clock input pin This is the system clock that drives the IC. However, in certain modes it is used as the interface switching pin. (See the timing charts.) Digital system power supply voltage pin Output pin for IC testing When low, digital audio data is input simultaneously from the DATAL and DATAR pins. When high, digital audio data is input from the DATA.