ICS843002I-72

www.DataSheet4U.com FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR ICS843002I-72 GENERAL DESCRIPTION The ICS843002I-72 is a member of the IC S HiperClockS™ family of high performance clock HiPerClockS™ solutions from IDT. The ICS843002I-72 is a PLL based synchronous clock generator that is optimized for WCDMA channel card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the second PLL stage. The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock™ VCO. The device performance and the PLL multiplication ratios are optimized to support WCDMA applications. The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given application. The ICS843002I-72 can accept a single-ended input. LOCK_DT reports the lock status of VCXO PLL loop. If the reference clock input is lost, it will set LOCK_DT to logic LOW. Typical ICS843002I-72 configuration in WCDMA Systems: 19.2MHz pullable crystal Input Reference clock frequency: 3.84MHz Output clock frequency: 122.88MHz ...