Document
TC74HC7292AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC7292AP, TC74HC7292AF
Programmable Divider/Timer
The TC74HC7292A is a high speed CMOS PROGRAMMABLE DIVIDER/TIMER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.
The TC74HC7292A can divide from 22 to 231. CK1 and CK2 are clock inputs, either one may be used for clock gating. It features an active-low clear input to initialize the state of all flip-flops. To facilitate incoming inspection, test points are provided. (TP1, TP2 and TP3) All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features
High speed: fmax = 70 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 4 μA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Output drive capability: 10 LSTTL loads Symmetrical output impedance: |IOH| = IOL = 4 mA (min) Balanced propagation delays: tpLH ∼− tpHL Wide operating voltage range: VCC (opr) = 2 to 6 V Pin and function compatible with 74LS292
Pin Assignment
TC74HC7292AP
TC74HC7292AF
Weight DIP16-P-300-2.54A SOP16-P-300-1.27A
: 1.00 g (typ.) : 0.18 g (typ.)
© 2001-2017
1
Toshiba Electronic Devices & Storage Corporation
Start of commercial production
1988-11
2017-09-21
IEC Logic Symbol
Truth Table
CLR CK1 CK2
L
X
X
H
L
H
L
H
H
X
H
X
H
Q Output Mode Cleared to L Up Count
No Change
TC74HC7292AP/AF
© 2001-2017
2
Toshiba Electronic Devices & Storage Corporation
2017-09-21
TC74HC7292AP/AF
Programming Inputs
E D C B A Binary
L L L L L Inhibit L L L L H Inhibit L L L H L 22 L L L H H 23 L L H L L 24 L L H L H 25 L L H H L 26 L L H H H 27 L H L L L 28 L H L L H 29 L H L H L 210 L H L H H 211 L H H L L 212 L H H L H 213 L H H H L 214 L H H H H 215 H L L L L 216 H L L L H 217 H L L H L 218 H L L H H 219 H L H L L 220 H L H L H 221 H L H H L 222 H L H H H 223 H H L L L 224 H H L L H 225 H H L H L 226 H H L H H 227 H H H L L 228 H H H L H 229 H H H H L 230 H H H H H 231
Frequency Division
Q
TP1
TP2
Decimal Binary
Decimal Binary
Decimal Binary
Inhibit Inhibit
Inhibit Inhibit
Inhibit Inhibit
Inhibit Inhibit 4 29 8 29
Inhibit Inhibit 512 217 512 217
Inhibit Inhibit 131,072 224 131,072 224
16 29 32 29 64 29 128 29
512 217 512 217 512 217 512 217
131,072 224 131,072 224 131,072 224 131,072 224
256 29 512 29 1,024 29 2,048 29
512 217 512 217 512 217 512 217
131,072 22 131,072 22 131,072 24 131,072 24
4,096 29 8,192 29 16,384 29 32,768 29
512 217 512 217 512 Disabled Low 512 Disabled Low
131,072 26 131,072 26
28 28
65,536 29 131,072 29 262,144 29 524,288 29
512 23 512 23 512 25 512 25
8 210 8 210 32 212 32 212
1,048,576 29 2,097,152 29 4,194,304 Disabled Low 8,388,608 Disabled Low
512 27 512 27
29 29
128 214 128 214 512 216 512 216
16,777,216 23 33,554,432 23 67,108,864 25 134,217,728 25
8 211 8 211 32 213 32 213
2,048 218 2,048 21.