EBE52UD6AFSA

DATA SHEET www.DataSheet4U.com 512MB DDR2 SDRAM SO-DIMM EBE52UD6AFSA (64M words × 64 bits, 2 Ranks) Description The EBE52UD6AFSA is 64M words × 64 bits, 2 ranks DDR2 SDRAM Small Outline Dual In-line Memory Module, mounting 8 pieces of 512M bits DDR2 SDRAM sealed in FBGA (µBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4 bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (µBGA) on the module board. Note: Do not push the components or drop the modules in order to avoid mechanical defects, which may result in electrical defects. Features 200-pin socket type small outline dual in line memory module (SO-DIMM)  PCB height: 30.0mm  Lead pitch: 0.6mm  Lead-free (RoHS compliant) Power supply: VDD = 1.8V ± 0.1V Data rate: 667Mbps/533Mbps/400Mbps (max.) SSTL_18 compatible I/O Double-data-rate architecture: two data transfers per clock cycle Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver DQS is edge aligned with data for READs: centeraligned with data f...