EBE51ED8AJWA

DATA SHEET www.DataSheet4U.com 512MB Unbuffered DDR2 SDRAM DIMM EBE51ED8AJWA (64M words × 72 bits, 1 Rank) Specifications Density: 512MB Organization  64M words × 72 bits, 1 rank Mounting 9 pieces of 512M bits DDR2 SDRAM sealed in FBGA Package: 240-pin socket type dual in line memory module (DIMM)  PCB height: 30.0mm  Lead pitch: 1.0mm  Lead-free (RoHS compliant) Power supply: VDD = 1.8V ± 0.1V Data rate: 800Mbps/667Mbps (max.) Four internal banks for concurrent operation (components) Interface: SSTL_18 Burst lengths (BL): 4, 8 /CAS Latency (CL): 3, 4, 5, 6 Precharge: auto precharge option for each burst access Refresh: auto-refresh, self-refresh Refresh cycles: 8192 cycles/64ms  Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C Operating case temperature range  TC = 0°C to +95°C Features Double-data-rate architecture; two data transfers per clock cycle The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver DQS is edge-aligned with data for READs; centeraligned with data for WRITEs Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Data mask (DM) for write data Posted /CAS by programmable additive latency for...