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256MB DDR2 SDRAM SO-DIMM
EBE25UD6ABSA (32M words × 64 bits, 1 Rank)
Description
The EBE25UD6ABSA is 32M words × 64 bits, 1 rank DDR2 SDRAM Small Outline Dual In-line Memory Module, mounting 4 pieces of 512M bits DDR2 SDRAM sealed in FBGA package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4 bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA on the module board. Note: Do not push the components or drop the modules in order to avoid mechanical defects, which may result in electrical defects.
Features
• 200-pin socket type small outline dual in line memory module (SO-DIMM) PCB height: 30.0mm Lead pitch: 0.6mm Lead-free • 1.8V power supply • Data rate: 533Mbps/400Mbps (max.) • 1.8V (SSTL_18 compatible) I/O • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs: centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation (Component) • Data mask (DM) for write data • Burst lengths: 4, 8 • /CAS Latency (CL): 3, 4, 5 • Auto precharge operation for each burst access • Auto refresh and self refresh modes • 7.8µs average periodic refresh interval • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • /DQS can be disabled for single-ended Data Strobe operation.
Document No. E0553E21 (Ver. 2.1) Date Published February 2006 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2004-2006
EBE25UD6ABSA
Ordering Information
Data rate Mbps (max.) 533 400 Component JEDEC speed bin (CL-tRCD-tRP) DDR2-533 (4-4-4) DDR2-400 (3-3-3) Contact pad
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Part number EBE25UD6ABSA-5C-E EBE25UD6ABSA-4A-E
Package
Mounted devices EDE5116ABSE-5C EDE5116ABSE-5C, -4A
200-pin SO-DIMM Gold (lead-free)
Pin Configurations
Front side 1 pin 39 pin 41 pin 199 pin
2 pin
40 pin 42 pin Back side
200 pin
Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 101 Pin name VREF VSS DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS /DQS2 A1 Pin No. 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91.