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EBE10UE8AFSA Dataheets PDF



Part Number EBE10UE8AFSA
Manufacturers Elpida Memory
Logo Elpida Memory
Description 1GB DDR2 SDRAM SO-DIMM
Datasheet EBE10UE8AFSA DatasheetEBE10UE8AFSA Datasheet (PDF)

DATA SHEET www.DataSheet4U.com 1GB DDR2 SDRAM SO-DIMM EBE10UE8AFSA (128M words × 64 bits, 1 Rank) Specifications • Density: 1GB • Organization  128M words × 64 bits, 1 rank • Mounting 8 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 200-pin socket type small outline dual in line memory module (SO-DIMM)  PCB height: 30.0mm  Lead pitch: 0.6mm  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps (max.) • Eight internal banks for c.

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DATA SHEET www.DataSheet4U.com 1GB DDR2 SDRAM SO-DIMM EBE10UE8AFSA (128M words × 64 bits, 1 Rank) Specifications • Density: 1GB • Organization  128M words × 64 bits, 1 rank • Mounting 8 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 200-pin socket type small outline dual in line memory module (SO-DIMM)  PCB height: 30.0mm  Lead pitch: 0.6mm  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps (max.) • Eight internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5, 6 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms  Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range  TC = 0°C to +95°C Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • /DQS can be disabled for single-ended Data Strobe operation Document No. E1450E20 (Ver.2.0) Date Published July 2009 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2009 EBE10UE8AFSA Ordering Information Data rate Mbps (max.) 800 667 Component JEDEC speed bin (CL-tRCD-tRP) DDR2-800 (6-6-6) DDR2-667 (5-5-5) Contact pad www.DataSheet4U.com Part number EBE10UE8AFSA-8G-F EBE10UE8AFSA-6E-F Package Mounted devices EDE1108AFSE-8E-F EDE1108AFSE-8G-F EDE1108AFSE-8E-F EDE1108AFSE-8G-F EDE1108AFSE-6E-F 200-pin SO-DIMM (lead-free and Gold halogen-free) Pin Configurations Front side 1 pin 39 pin 41 pin 199 pin 2 pin 40 pin 42 pin Back side 200 pin Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Pin name VREF VSS DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS /DQS2 Pin No. 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Pin name DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 Back side Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Pin name VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 /CK0 VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC Pin No. 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Pin name DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS /DQS3 DQS3 VSS DQ30 DQ31 VSS NC VDD NC NC VDD A11 A7 A6 VDD A4 A2 Data Sheet E1450E20 (Ver. 2.0) 2 EBE10UE8AFSA Front side Pin No. 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Pin name A1 VDD A10/AP BA0 /WE VDD /CAS NC VDD NC VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS Pin No. 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Pin name DQ42 DQ43 VSS DQ48 DQ49 VSS NC VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD Back side Pin No. 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Pin name A0 VDD BA1 /RAS /CS0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS /DQS5 DQS5 VSS Pin No. 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 www.DataSheet4U.com Pin name DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 /CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS /DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1 Data Sheet E1450E20 (Ver. 2.0) 3 EBE10UE8AFSA Pin Description Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 /RAS /CAS /WE /CS0 CKE0 CK0, CK1 /CK0, /CK1 DQS0 to DQS7, /DQS0 to /DQS7 DM0 to DM7 SCL SDA SA0, SA1 VDD VDDSPD VREF VSS ODT0 NC Function Address input Row address Column address Auto precharge Bank select address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground ODT control No connection A0 to A13 A0 to A9 www.DataSheet4U.com Data Sheet E1450E20 (Ver. 2.0) 4 EBE10UE8AFSA Serial PD Matrix Byte No. Function described 0 1 2 3 4.


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