MAX9218

19-3557; Rev 1; 4/05 www.DataSheet4U.com 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer General Description The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take advantage of video timing to reduce the serial data rate. The MAX9218 pairs with the MAX9217 serializer to form a complete digital video transmission system. Proprietary data decoding reduces EMI and provides DC balance. The DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The MAX9218 features a selectable rising or falling output latch edge. ESD tolerance is specified for ISO 10605 with ±10kV contact discharge and ±30kV air discharge. The MAX9218 operates from a +3.3V core supply and features a separate output supply for interfacing to 1.8V to 3.3V logic-level inputs. This device is available in 48lead Thin QFN and TQFP packages and is specified from -40°C to +85°C. Features ♦ Proprietary Data Decoding for DC Balance and Reduced EMI ♦ Control Data Deserialized During Video Blanking ♦ Five Control Data Inputs Are Single Bit-Error Tolerant ♦ Output Transition Time Is Scaled to Operating Frequency for Reduced EMI ♦ Staggered Output Switching Reduces EMI ♦ Output Enable All...