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IDT5T907 2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
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2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER™
FEATURES:
• • • • • • • • •
IDT5T907
DESCRIPTION:
Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion High speed propagation delay < 2.5ns. (max) Up to 250MHz operation Very low CMOS power levels 1.5V VDDQ for HSTL interface Hot insertable and over-voltage tolerant inputs 3-level inputs for selectable interface Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface • Selectable differential or single-ended inputs and ten singleended outputs • 2.5V VDD • Available in TSSOP package
The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to ten single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to ten single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The IDT5T907 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The IDT5T907 has two output banks that can be asynchronously enabled/ disabled. Multiple power and grounds reduce noise.
• Clock and signal distribution
APPLICATIONS:
FUNCTIONAL BLOCK DIAGRAM
TxS GL G1
O UTPUT CO NTR OL
Q1
O UTPUT CO NTR OL
Q2
O UTPUT CO NTR OL
Q3
RxS A A/V R EF
O UTPUT CO NTR OL
Q4
O UTPUT CO NTR OL
Q5
G2
O UTPUT CO NTR OL
Q6
O UTPUT CO NTR OL
Q7
O UTPUT CO NTR OL
Q8
O UTPUT CO NTR OL
Q9
O UTPUT CO NTR OL
Q 10
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
FEBRUARY 2003
DSC-5899/22
© 2003 Integrated Device Technology, Inc.
IDT5T907 2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
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PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD Description Power Supply Voltage(2) Output Power Input Voltage Output Voltage(3) Reference Voltage(3) Storage Temperature Junction Temperature Supply(2) Max –0.5 to +3.6 –0.5 to +3.6 –0.5 to +3.6 –0.5 to VDDQ +0.5 –0.5 to +3.6 –65 to +165 150 Unit V V V V V °C °C VDDQ VI VO VREF TSTG TJ
GL V DD V DD GND GND G1 V DDQ Q2 Q1 GND V DDQ A/V REF A V DDQ GND Q 10 Q9 V DDQ G2 GND GND V DD V DD RxS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND V DDQ V DDQ GND GND GND V DDQ Q3 Q4 GND V DDQ Q5 Q6 V DDQ GND Q7 Q8 V DDQ V DDQ GND GND V DDQ GND TxS
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met. 3. Not to exceed 3.6V.
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)
Symbol CIN Parameter Input Capacitance Min Typ. 3.5 Max. Unit pF
—
—
NOTE: 1. This parameter is measured at characterization but not tested. Capacitance applies to all inputs except RxS and TxS.
TSSOP TOP VIEW
RECOMMENDED OPERATING RANGE
Symbol TA VDD(1) VDDQ(1) VT Description Ambient Operating Temperature Internal Power Supply Voltage HSTL Output Power Supply Voltage Extended HSTL and 1.8V LVTTL Output Power Supply Voltage 2.5V LVTTL Output Power Supply Voltage Termination Voltage Min. –40 2.4 1.4 1.65 Typ. +25 2.5 1.5 1.8 VDD VDDQ / 2 Max. +85 2.6 1.6 1.95 Unit °C V V V V V
NOTE: 1. All power supplies should operate in tandem; if VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at a maximum, and vice-versa.
2
IDT5T907 2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
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PIN DESCRIPTION
Symbol A A/VREF I/O I I Type Adjustable(1) Adjustable(1) Description Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input. Complementary clock input. A/VREF is the "complementary" side of A if the input is in differential mode. If operating in single-ended mode, A/VREF is connected to GND. For single-ended operation in differential mode, A/VREF should be set to the desired toggle voltage for A: 2.5V LVTTL VREF = 1250mV 1.8V LVTTL, eHSTL VREF = 900mV HSTL VREF = 750mV LVEPECL VREF = 1082mV Gate for outputs Q1 through Q5. When G1 is LOW, these outputs are enabled. When G1 is HIGH, these outputs are asynchronously disabled to the level designated by GL(4). Gate for outputs Q6 through Q10. W.