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IDT723653 Dataheets PDF



Part Number IDT723653
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description (IDT7236x3) CMOS SyncFIFO WITH BUS-MATCHING
Datasheet IDT723653 DatasheetIDT723653 Datasheet (PDF)

CMOS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36 4,096 x 36 8,192 x 36 www.DataSheet4U.com IDT723653 IDT723663 IDT723673 FEATURES • • • • • • • Memory storage capacity: IDT723653 – 2,048 x 36 IDT723663 – 4,096 x 36 IDT723673 – 8,192 x 36 Clock frequencies up to 83 MHz (8 ns access time) Clocked FIFO buffering data from Port A to Port B IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions) Programmable Almost-Empty and Almost-Full flags; each ha.

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CMOS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36 4,096 x 36 8,192 x 36 www.DataSheet4U.com IDT723653 IDT723663 IDT723673 FEATURES • • • • • • • Memory storage capacity: IDT723653 – 2,048 x 36 IDT723663 – 4,096 x 36 IDT723673 – 8,192 x 36 Clock frequencies up to 83 MHz (8 ns access time) Clocked FIFO buffering data from Port A to Port B IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions) Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024) Serial or parallel programming of partial flags Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte) • • • • • • • • • • Big- or Little-Endian format for word and byte bus sizes Retransmit Capability Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Easily expandable in width and depth Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin compatible with the lower density parts, IDT723623/723633/ 723643 Industrial temperature range (–40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register Port-A Control Logic BusMatching Input Register Output Register 36 CLKA CSA W/RA ENA MBA RS1 RS2 PRS RAM ARRAY 36 FIFO1 Mail1, Mail2, Reset Logic 36 2,048 x 36 4,096 x 36 8,192 x 36 36 RT RTM FIFO Retransmit Logic Write Pointer Read Pointer B0-B35 A0-A35 FF/IR AF Status Flag Logic EF/OR AE 36 36 FS2 FS0/SD FS1/SEN Programmable Flag Offset Registers 13 Timing Mode Port-B Control Logic Mail 2 Register MBF2 FWFT CLKB CSB W/RB ENB MBB BE BM SIZE 5610 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2003 DSC-5610/4 IDT723653/723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DESCRIPTION The IDT723653/723663/723673 is a monolithic, high-speed, low-power, CMOS unidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8ns. The 2,048/4,096/8,192 x 36 dual-port SRAM FIFO buffers data from Port A to Port B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations. These devices are synchronous (clocked) FIFOs, meaning each port www.DataSheet4U.com employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are.


IDT723663 IDT723653 IDT723673


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