DatasheetsPDF.com

MC100ES8111 Dataheets PDF



Part Number MC100ES8111
Manufacturers Motorola
Logo Motorola
Description Low Voltage 1:10 Differential HSTL Clock Fanout Buffer
Datasheet MC100ES8111 DatasheetMC100ES8111 Datasheet (PDF)

Freescale Semiconductor Technical Data MC100ES8111 Rev 2, 09/2004 www.DataSheet4U.com Low Voltage 1:10 Differential HSTL Clock Fanout Buffer The MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES8111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs a.

  MC100ES8111   MC100ES8111



Document
Freescale Semiconductor Technical Data MC100ES8111 Rev 2, 09/2004 www.DataSheet4U.com Low Voltage 1:10 Differential HSTL Clock Fanout Buffer The MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES8111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. Features • • • • • • • • • 1:10 differential clock fanout buffer 80 ps maximum device skew SiGe technology Supports DC to 625 MHz operation of clock or data signals HSTL compatible differential clock outputs PECL and HSTL compatible differential clock inputs 3.3 V power supply for device core, 1.5 V or 1.8 V HSTL output supply Supports industrial temperature range Standard 32 lead LQFP package MC100ES8111 LOW-VOLTAGE 1:10 DIFFERENTIAL HSTL CLOCK FANOUT BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MC100ES8111 is designed for low skew clock distribution systems and supports clock frequencies up to 625 MHz. The device accepts two clock sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential HSTL compatible outputs. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all 10 outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The HSTL compatible output levels are generated with an open emitter architecture. This minimizes part-to-part and output-to-output skew. The open-emitter outputs require a 50 Ω DC termination to GND (0 V). The output supply voltage can be either 1.5 V or 1.8 V, the core voltage supply is 3.3 V. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm 2 32-lead LQFP package. © Freescale Semiconductor, Inc., 2004. All rights reserved. Freescale Confidential Proprietary, NDA Required / Preliminary Q3 Q4 Q4 Q5 Q5 Q6 18 VCC CLK0 CLK0 0 VCC CLK1 CLK1 1 OE CLK_SEL Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 www.DataSheet4U.com 24 VCCO Q2 Q2 Q1 Q1 Q0 Q0 VCCO 25 26 27 28 29 30 31 32 1 23 22 21 20 19 Q6 17 Q3 16 15 14 13 VCC0 Q7 Q7 Q8 Q8 Q9 Q9 VCCO MC100ES8111 12 11 10 9 .


MC100ES7111 MC100ES8111 ES7134


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)