NB7V585M

NB7V585M 1.8V / 2.5V Differential 2:1 Mux Input to 1:6 CML Clock/Data Fanout Buffer/Translator Description Multi−Level Inputs w/ Internal Termination The NB7V585M is a differential 1 −to −6 CML clock/data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INx inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels (see Figure 9). The NB7V585M produces six identical output copies of clock or data operating up to 6 GHz or 10 Gb/s, respectively. As such, NB7V585M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. The 16 mA differential CML output structure provides matching internal 50 W source terminations, 400 mV output swings when externally terminated with a 50 W resistor to VCC (see Figure 14) and is optimized for low skew and minimal jitter. The NB7V585M is powered with either 1.8 V or 2.5 V supply and is offered in a low profile 5x5 mm 32−pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7V585M is a member of the GigaComm™ family of high performance clock products. http://onsemi.com MARKING DIAGRAM* 1 1 32 QFN32 MN SUFFIX CASE 488AM NB7V 585M AWLYYWW G A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. Maximum Input Data Rate > 10 Gb/s Data Dependent Jitter...