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K5L5628JBM Dataheets PDF



Part Number K5L5628JBM
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM
Datasheet K5L5628JBM DatasheetK5L5628JBM Datasheet (PDF)

www.DataSheet4U.com K5L5628JT(B)M Document Title Multi-Chip Package MEMORY Preliminary Preliminary MCP MEMORY 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM Revision History Revision No. History 0.0 Initial Draft (256M NOR Flash A-die_rev0.3) (128M UtRAM M-die_rev0.1) Finalize .. rev 1.0 - Deleted Synchronous Burst Read and Asynchronous Write Mode Draft Date August 12, 2004 Remark Preliminary 1.0 November 10, 2004 Final.

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www.DataSheet4U.com K5L5628JT(B)M Document Title Multi-Chip Package MEMORY Preliminary Preliminary MCP MEMORY 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM Revision History Revision No. History 0.0 Initial Draft (256M NOR Flash A-die_rev0.3) (128M UtRAM M-die_rev0.1) Finalize ....... rev 1.0 - Deleted Synchronous Burst Read and Asynchronous Write Mode Draft Date August 12, 2004 Remark Preliminary 1.0 November 10, 2004 Final Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site. http://samsungelectronics.com/semiconductors/products/products_index.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. 1 Revision 1.0 November 2004 www.DataSheet4U.com K5L5628JT(B)M Multi-Chip Package MEMORY Preliminary Preliminary MCP MEMORY 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM FEATURES • Operating Temperature : -30°C ~ 85°C • Package : 115Ball FBGA Type - 8.0mm x 12.0mm 0.8mm ball pitch 1.4mm (Max.) Thickness • Single Voltage, 1.7V to 1.95V for Read and Write operations • Organization - 16,772,216 x 16 bit ( Word Mode Only) • Read While Program/Erase Operation • Multiple Bank Architecture - 16 Banks (16Mb Partition) • OTP Block : Extra 256Byte block • Read Access Time (@ CL=30pF) - Asynchronous Random Access Time : 90ns (54MHz) / 80ns (66MHz) - Synchronous Random Access Time : 88.5ns (54MHz) / 70ns (66MHz) - Burst Access Time : 14.5ns (54MHz) / 11ns (66MHz) • Burst Length : - Continuous Linear Burst - Linear Burst : 8-word & 16-word with No-wrap & Wrap • Block Architecture - Eight 4Kword blocks and five hundreds eleven 32Kword blocks - Bank 0 contains eight 4 Kword blocks and thirty-one 32Kword blocks - Bank 1 ~ Bank 15 contain four hundred eighty 32Kword blocks • Reduce program time using the VPP • Support Single & Quad word accelerate program • Power Consumption (Typical value, CL=30pF) - Burst Access Current : 30mA - Program/Erase Current : 15mA - Read While Program/Erase Current : 40mA - Standby Mode/Auto Sleep Mode : 25uA • Block Protection/Unprotection - Using the software command sequence - Last two boot blocks are protected by WP=VIL - All blocks are protected by VPP=VIL • Handshaking Feature - Provides host system with minimum latency by monitoring RDY • Erase Suspend/Resume • Program Suspend/Resume • Unlock Bypass Program/Erase • Hardware Reset (RESET) • Data Polling and Toggle Bits - Provides a software method of detecting the status of program or erase completion • Endurance 100K Program/Erase Cycles Minimum • Data Retention : 10 years • Support Common Flash Memory Interface • Low Vcc Write Inhibit • Process Technology: CMOS • Organization: 8M x16 bit • Power Supply Voltage: VCC 2.5~2.7V, VCCQ 1.7~2.0V • Three State Outputs • Supports MRS (Mode Register Set) • MRS control - MRS Pin Control • Supports Power Saving modes - Partial Array Refresh mode Internal TCSR • Supports Driver Strength Optimization for system environment power saving. • Supports Asynchronous 4-Page Read and Asynchronous Write Operation • Supports Synchronous Burst Read and Synchronous Burst Write Operation • Synchronous Burst(Read/Write) Operation - Supports 4 word / 8 word / 16 word and Full Page(256 word) burst - Supports Linear Burst type & Interleave Burst type - Latency support : Latency 3 @ 52.9MHz(tCD 12ns) - Supports Burst Read Suspend in No Clock toggling - Supports Burst Write Data Masking by /UB & /LB pin control - Supports WAIT pin function for indicating data availability. • Max. Burst Clock Frequency : 52.9MHz SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 November 2004 www.DataSheet4U.com K5L5628JT(B)M GENERAL DESCRIPTION Preliminary Preliminary MCP MEMORY The K5L5628JT(B)M is a Multi Chip Package Memory which combines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory and 128Mbit Synchronous Burst UtRAM. 256Mbit Synchronous Burst Multi Bank NOR Flash Memory is organized as 16M x16 bits and 128Mbit Synchronous Burst UtRAM is organized as 8M x16 bits. In 256Mbit Synchronous Burst Multi Bank NOR Flash Memory, the memory architecture of the device is designed to divide its memory arrays into 519 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capability. The NOR Flash consists of sixteen banks. This device is capable of reading data from one bank while programming or erasing in the other bank. Regarding read access time, the device provides an 14.5ns burst access time and an 88.5ns initial access time at.


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