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STLS2F01
High performance 64-bit superscalar
Features
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MIPS®
Loongson 2F: microprocessor
Preliminary Data
64-bit superscalar architecture 900 MHz clock frequency Single/double precision floating-point units New streaming multimedia instruction set support (SIMD) 64 Kbyte instruction cache, 64 Kbyte data cache, on-chip 512 Kbyte unified L2 cache On chip DDR2-667 and PCI-X controller 4 W @ 900 MHz power consumption: – Best in class for power management – Voltage/frequency scaling – Stand-by mode support – L2 cache disable/enable option Leading edge 90 nm process technology 27x27 heat spreader flip-chip BGA package MIPS based instruction set (MIPS III compatible)
HFCBGA452 (27x27x2.9mm)
The memory hierarchy is composed by the first level of 64 Kbyte 4-way set associative caches for instructions and data, the second level of 512 Kbyte unified 4-way set associative cache and the memory management unit (MMU) with translation lookaside buffer (TLB). The Loongson microprocessor family is the outcome of a successful collaboration started in 2004 between STMicroelectronics and the Institute of Computing Technology, part of the Chinese Academy of Science. Loongson microprocessors were co-developed by STMicroelectronics and the Institute of Computing Technology to address all the applications requiring high level of performance and low power dissipation. Compared to the STLS2E02 processor, the STLS2F01 has an enhanced architecture providing higher performance, reduced power consumption, integrated DDR2 memory controller and PCI-X bus interface.
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Description
The STLS2F01 is a MIPS based 64-bit superscalar microprocessor, able to issue four instructions per clock cycle among six functional units: two integer, two single/double-precision floating-point, one 64bit SIMD and one load/store unit. The micro architecture is organized with ninestage of pipeline and support of dynamic branch prediction. Table 1. Device summary
Part numbers STLS2F01
Package HFCBGA452 (27x27x2.9mm)
Packing Tray
May 2008
Rev 1
1/48
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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Contents
STLS2F01
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 Interface signal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PCI bus interface signal components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DDR2 SDRAM interface signal components . . . . . . . . . . . . . . . . . . . . . . 10 Local bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Initialization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test and control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
I/O bus interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 3.2 3.3 3.4 3.5 3.6 PCI interface characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Host and agent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PCI bus arbitrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Local bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
DDR2 SDRAM controller interface description . . . . . . . . . . . . . . . . . . 21
4.1 4.2 4.3 4.4 4.5 DDR2 SDRAM controller features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DDR2 SDRAM read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DDR2 SDRAM write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DDR2 SDRAM parameter format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DDR2 SDRAM sample mode configuration . . . . . . . . . . . . . . . . . . . . . . . 34
5 6
Initialization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..