CS2100-CP

www.DataSheet4U.com CS2100-CP Fractional-N Clock Multiplier General Description The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock at frequencies as low as 50 Hz. The CS2100-CP supports both I²C and SPI for full software control. The CS2100-CP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) grade. Customer development kits are also available for device evaluation. Please see “Ordering Information” on page 32 for complete details. Features  Clock Multiplier / Jitter Reduction      Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in HighResolution Mode ® I²C / SPI™ Control Port Configurable Auxiliary Output Flexible Sourcing of Reference Clock – External Oscillator or Clock Source – Supports Inexpensive Local Crystal Minimal Board Space Required – No External Analog Loop-filter Components – 3.3 V Timing Reference Frequency Reference PLL Output Lock Indicator I²C/SPI Software Control I²C / SPI Auxiliary Output 8 MHz to 75 MHz Low-Jitter Timing Reference Fractional-N Frequency Syn...