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CDRM622 Dataheets PDF



Part Number CDRM622
Manufacturers Agere Systems
Logo Agere Systems
Description 622 Mbits/s Multichannel Digital Timing Recovery
Datasheet CDRM622 DatasheetCDRM622 Datasheet (PDF)

Data Sheet June 1999 www.DataSheet4U.com CDRM622 622 Mbits/s Multichannel Digital Timing Recovery Features s Description The CDRM622 provides a physical medium for highspeed asynchronous serial data transfer between ASIC devices. Devices can be on the same PCboard, or on separate boards connected across a backplane, or connected by cables. The macrocell is intended for, but not limited to, terminal equipment in SONET/SDH and ATM systems. The macrocell consists of three functional blocks. The r.

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Data Sheet June 1999 www.DataSheet4U.com CDRM622 622 Mbits/s Multichannel Digital Timing Recovery Features s Description The CDRM622 provides a physical medium for highspeed asynchronous serial data transfer between ASIC devices. Devices can be on the same PCboard, or on separate boards connected across a backplane, or connected by cables. The macrocell is intended for, but not limited to, terminal equipment in SONET/SDH and ATM systems. The macrocell consists of three functional blocks. The receiver accepts 622.08 Mbits/s serial data. Based on data transitions, the receiver selects an appropriate 622 MHz clock phase for each channel to retime the data, then demultiplexes down to 77.76 Mbytes/s parallel bytes and a 77.76 MHz clock. The transmitter operates in the reverse direction. 77.76 Mbytes/s parallel bytes are multiplexed up to 662.08 Mbits/s serial data for off-chip communication. The clock synthesizer generates the necessary 622.08 MHz clock for operation from a 77.76 MHz reference. Figure 1 illustrates the function of the macrocell. The hard macrocell can be supplied for up to 16 data channels. Multiple macrocells can be used on a single device. The macrocell is intended to be used with high-speed differential I/O buffers for the 622 Mbits/s serial data streams and the 77.76 MHz reference clock. Common selections are low-voltage differential swing (LVDS) or PECL. The I/O buffers are part of our standard-cell ASIC library and are not included in the macrocell to allow for flexibility. Receives scrambled serial data at STS-12/STM-4 (622.08 Mbits/s) rate. Demultiplexes serial data to 77.76 Mbytes/s parallel byte wide data with aligned 77.76 MHz clock. Synthesizes 622.06 MHz clock with on-chip PLL, requiring only 77.76 MHz input reference clock and one external resistor. Multiplexes parallel 77.76 Mbytes/s data to 622 Mbits/s serial data for transmission. Incorporates n = 1 to 16 channels with modular design. Implemented in Lucent Technologies Microelectronics Group HL250C technology. Meets type B jitter tolerance specification of ITU-T Recommendation G.958. Sources stable clock in absence of data transitions once the clock synthesizer has acquired lock. Uses single, low-voltage (3.3 V ± 5%) supply. Includes built-in test circuitry such as high-speed loopback of transmit data into receiver. IDDQ compatible. Powers down the receiver on per-channel basis. Allows JTAG access to high-speed data paths. s s s s s s s s s s s CDRM622 622 Mbits/s Multichannel Digital Timing Recovery Macrocell www.DataSheet4U.com Data Sheet June 1999 Description (continued) MRESET (MASTER RESET) TSTMODE TSTSHFTLD ECSEL EXDNUP ETOGGLE TSTPHASE BUILT-IN TEST TSTMUX[8:0] Rx TSTCLK BYPASS LOOPBKEN LOOPBKCH[(n – 1):0] HDIN[(n – 1):0] 622 Mbits/s DATA CDR CLOCK/DATA ALIGNMENT RETIME SELECT SERIAL TO PARRALLEL (622 Mbits/s TO 78 Mbytes/s) DEMUX 1 2 n BSIPAD[(n – 1):0] (BOUNDARY SCAN) LD[(n – 1):0]R[7:0] 77.76 Mbytes/s LCKR[(n – 1):0] 77.76 MHz RESETRN .


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