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ADCLK854 Dataheets PDF



Part Number ADCLK854
Manufacturers Analog Devices
Logo Analog Devices
Description Low Power Clock Fanout Buffer
Datasheet ADCLK854 DatasheetADCLK854 Datasheet (PDF)

www.DataSheet4U.com 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer ADCLK854 FUNCTIONAL BLOCK DIAGRAM ADCLK854 VREF CLK0 CLK0 CLK1 CLK1 IN_SEL CTRL_A LVDS/ CMOS VS/2 LVDS/ CMOS OUT0 (OUT0A) OUT0 (OUT0B) OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B) FEATURES 2 selectable differential inputs Selectable LVDS/CMOS outputs Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs <12 mW per channel (100 MHz operation) 54 fs rms integrated jitter (12 kHz to 20.

  ADCLK854   ADCLK854


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www.DataSheet4U.com 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer ADCLK854 FUNCTIONAL BLOCK DIAGRAM ADCLK854 VREF CLK0 CLK0 CLK1 CLK1 IN_SEL CTRL_A LVDS/ CMOS VS/2 LVDS/ CMOS OUT0 (OUT0A) OUT0 (OUT0B) OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B) FEATURES 2 selectable differential inputs Selectable LVDS/CMOS outputs Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs <12 mW per channel (100 MHz operation) 54 fs rms integrated jitter (12 kHz to 20 MHz) 100 fs rms additive broadband jitter 2.0 ns propagation delay (LVDS) 135 ps output rise/fall (LVDS) 70 ps output-to-output skew (LVDS) Sleep mode Pin programmable control 1.8 V power supply APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation CTRL_B OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B) GENERAL DESCRIPTION The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs. The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device. The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection. This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C. LVDS/ CMOS OUT8 (OUT8A) OUT8 (OUT8B) OUT9 (OUT9A) CTRL_C OUT9 (OUT9B) OUT10 (OUT10A) OUT10 (OUT10B) SLEEP OUT11 (OUT11A) 07218-001 OUT11 (OUT11B) Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. www.DataSheet4U.com ADCLK854 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Electrical Characteristics ............................................................. 3  Timing Characteristics ................................................................ 4  Clock Characteristics ................................................................... 5  Logic and Power Characteristics ................................................ 5  Absolute Maximum Ratings............................................................ 6  Determining Junction Temperature .......................................... 6  ESD Caution .................................................................................. 6  Thermal Performance .................................................................. 6  Pin Configuration and Function Descriptions ............................. 7  Typical Performance Characteristics ..............................................9  Functional Description .................................................................. 12  Clock Inputs ................................................................................ 12  AC-Coupled Input Applications............................................... 12  Clock Outputs ............................................................................. 12  Control and Function Pins........................................................ 13  Power Supply............................................................................... 13  Applications Information .............................................................. 14  Using the ADCLK854 Outputs for ADC Clock Applications ............................


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