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DEVICE SPECIFICATION
QUAD GIGABIT ETHERNET DEVICE QUAD GIGABIT ETHERNET DEVICE GENERAL DESCRIPTION
S2204 S2204
FEATURES
• 1250 MHz (Gigabit Ethernet) operating rate www.datasheet4u.com - 1/2 Rate Operation • Quad Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference • Quad Receiver PLL provides clock and data recovery • Internally series terminated TTL outputs • Low-jitter serial PECL interface • Individual local loopback control • JTAG 1149.1 Boundary scan on low speed I/O signals • Interfaces with coax, twinax, or fiber optics • Single +3.3V supply, 2.5 W power dissipation • Compact 23mm x 23mm 208 TBGA package
The S2204 facilitates high-speed serial transmission of data in a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point to point links. The chip provides four separate transceivers which can be operated individually for a data capacity of >4 Gbps. Each bi-directional channel provides parallel to serial and serial to parallel conversion, clock generation/ recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip quad receive PLL is used for clock recovery and data re-timing on the four independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 2.5 watts. Figure 1 shows the S2204 and S2004 in a Gigabit Ethernet application. Figure 2 combines the S2204 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/ output diagram. Figures 4 and 5 show the transmit and receive block diagrams, respectively.
APPLICATIONS
• • • • • • Ethernet Backbones Workstation Frame buffer Switched networks Data broadcast environments Proprietary extended backplanes
Figure 1. Typical Quad Gigabit Ethernet Application
GE INTERFACE SERIAL BP DRIVER
MAC
(ASIC)
QUAD GIGABIT ETHERNET INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2204 MAC
(ASIC)
S2004
MAC
(ASIC)
July 16, 1999 / Revision C
1
S2204
Figure 2. Typical Backplane Application
MAC
www.datasheet4u.com
(ASIC)
QUAD GIGABIT ETHERNET DEVICE
MAC
(ASIC)
MAC ATM Ethernet Etc.
(ASIC)
MAC
(ASIC)
S2204 MAC
(ASIC)
S2004
S2004 MAC
(ASIC)
S2204
ATM Ethernet Etc.
MAC
(ASIC)
MAC
(ASIC)
Crosspoint Switch S2016 S2025 MAC
(ASIC)
MAC
(ASIC)
ATM Ethernet Etc.
MAC
(ASIC)
MAC
(ASIC)
S2204 MAC
(ASIC)
S2004
S2004 MAC
(ASIC)
S2204
ATM Ethernet Etc.
MAC
(ASIC)
BACKPLANE SIGNAL GROUP
MAC
(ASIC)
2
July 16, 1999 / Revision C
QUAD GIGABIT ETHERNET DEVICE
Figure 3. S2204 Input/Output Diagram
TRS TMS TCK TDI TDO
S2204
www.datasheet4u.com
RESET RATE
REFCLK CLKSEL TMODE
TXAP/N
TCLKO TXBP/N DINA[0:9] TBCA TXCP/N DINB[0:9] TBCB
10 10
DINC[0:9] TBCC
10
TXDP/N
DIND[0:9] TBCD COM_DETA DOUTA[0:9] RBC1/0A
10
RXAP/N
10
RXBP/N COM_DETB DOUTB[0:9] RBC1/0B RXCP/N COM_DETC DOUTC[0:9] RBC1/0C COM_DETD DOUTD[0:9] RBC1/0D
10 10 10
RXDP/N
TESTMODE TESTMODE1 CMODE
LPENA LPENB LPENC LPEND
July 16, 1999 / Revision C
3
S2204
Figure 4. Transmitter Block Diagram
RATE REFCLK www.datasheet4u.com CLKSEL
DIN PLL 10x/20x
QUAD GIGABIT ETHERNET DEVICE
REFCLK
TCLKO TMODE TMODE 10 DINA[0:9] FIFO
(input)
10
Shift Reg
TXAP TXAN TXABP
0 1
TBCA 10 DINB[0:9] FIFO
(input)
10
Shift Reg
TXBP TXBN TXBBP
0 1
TBCB 10 DINC[0:9] FIFO
(input)
10
Shift Reg
TXCP TXCN TXCBP
0 1
TBCC 10 DIND[0:9] FIFO
(input)
10 TXDP
Shift Reg
TXDN TXDBP
0 1
TBCD
4
July 16, 1999 / Revision C
QUAD GIGABIT ETHERNET DEVICE
Figure 5. Receiver Block Diagram
TMODE
S2204
CMODE
www.datasheet4u.com RATE
REFCLK RBC1/0A COM_DETA
2 TXABP FIFO
(output) 10
10 DOUTA[0:9] Q
DOUT CRU SerialParallel
RXAP RXAN LPENA
2 RBC1/0B COM_DETB FIFO
(output) 10
TXBBP
DOUT CRU SerialParallel
10 DOUTB[0:9]
RXBP RXBN
RBC1/0C COM_DETC
2
LPENB
FIFO
(output)
TXCBP
10
10 DOUTC[0:9]
DOUT CRU SerialParallel
RXCP RXCN
LPENC RBC1/0D COM_DETD FIFO
(output) 10
2 TXDBP
DOUT CRU SerialParallel
10 DOUTD[0:9]
RXDP RXDN
LPEND
July 16, 1999 / Revision C
5
S2204 TRANSMITTER DESCRIPTION
The transmitter section of the S2204 contains a single PLL which is used to generate the serial rate transmit clock for all transmitters. Four channels are www.datasheet4u.com provided with a variety of options regarding input clocking and loopback. The transmitters operate at 1.250 GHz, 10 or 20 times the reference clock frequency.
QUAD GIGABIT ETHERNET DEVICE
Figure 6 demonstrates the flexibility afforded by the S2204. A low jitter reference is provided directly to the S2204 at either 1/10 or 1/20 the serial data rate. This insures minimum jitter in the synthesized clock used for serial data transmission. A system clock output at the parallel word rate, TCLKO, is derived from the PLL and provided to the upstream circuit as a system clock. Th.