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SAE81C80A Dataheets PDF



Part Number SAE81C80A
Manufacturers Siemens
Logo Siemens
Description CMOS Dual Port RAM
Datasheet SAE81C80A DatasheetSAE81C80A Datasheet (PDF)

www.DataSheet4U.com CMOS Dual-Port RAM SAE 81C80 A CMOS IC Features q q q q q q q q q q q q q q q Processor interface with address and data bus plus signals ALE, WR, RD 8051-, 8096-compatible timing Memory capacity 504 bytes All functions fully static (excl. oscillator watchdog) Standby operation On-chip oscillator with separate clock output Eight scheduling registers Three loadable timers for processor monitoring or applicable as longterm timers Monitoring of internal oscillator (hardware w.

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www.DataSheet4U.com CMOS Dual-Port RAM SAE 81C80 A CMOS IC Features q q q q q q q q q q q q q q q Processor interface with address and data bus plus signals ALE, WR, RD 8051-, 8096-compatible timing Memory capacity 504 bytes All functions fully static (excl. oscillator watchdog) Standby operation On-chip oscillator with separate clock output Eight scheduling registers Three loadable timers for processor monitoring or applicable as longterm timers Monitoring of internal oscillator (hardware watchdog) Three outputs for interrupt triggering (can be set on the bus) Fully asynchronous operation of two processors possible Data retention down to 1 V P-LCC-44 (SMD) package Extended temperature range from – 40 through 110 °C CMOS technology Ordering Code Q67100-H8706 P-LCC-44-1 Type SAE 81C80 A Package P-LCC-44-1 (SMD) The SAE 81C80 A dual-port RAM (DPR) is a CMOS memory IC with a capacity of 504 bytes (figure 1). A very notable feature of this DPR is that it can be used by two microcontrollers (MCs) simultaneously and fully asynchronously. Each microcontroller uses the DPR like a normal static RAM. Thus, when comparing the circuit development of this DPR with that of standard memory, no extra effort is required. Access collisions are excluded, which is the pre-requisite for fast communication between the two MCs. The SAE 81C80 A DPR is ideally suited for multi-processor/multi-controller applications like master/slave configurations or controls where one controller aquires measured data and a second one controls the actuators (e.g. in motors, etc.). (See figures 2 and 3). Semiconductor Group 1 09.94 SAE 81C80 A www.DataSheet4U.com Pin Configuration (top view) Semiconductor Group 2 SAE 81C80 A www.DataSheet4U.com Pin Definitions and Functions Pin No. 7 8 9 10 11 12 13 14 06 37 36 35 34 33 32 31 30 38 15 29 Symbol Function AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 A18 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 A28 ALE1 ALE2 Data and address bus port 1 Address 8 port 1 Data and address bus port 2 Address 8 port 1 Address latch enable port 1 Address latch enable port 2 These signals are for separating data and addresses on the bus. The address is stored on the falling edge of the signal. Read signal port 1 (active low) Read signal port 2 (active low) Write signal port 1 (active low) Write signal port 2 (active low) Chip select port 1 Chip select port 1 (active low) Chip select port 2 Chip select port 2 (active low) The chip-select inputs select a port when the two associated inputs are on active level. 5 39 4 40 3 2 41 42 RD1 RD2 WR1 WR2 CS1 CS1 CS2 CS2 Semiconductor Group 3 SAE 81C80 A www.DataSheet4U.com Pin No. 27 Symbol Function RES Reset input Resets the IC to a defined initial state when RES is low. At the same time the outputs WD1, WD2, WD3 are switched low for the duration of the reset pulse. The oscillator continues to operate. Power down Disables all other inputs and the oscillator when PD is low. Negative supply voltage Positive supply voltage Not connected Pin for crystal (must remain open for external clock supply). Pin for crystal or applying external clock Clock output Oscillator watchdog (open-drain output) High indicates that the oscillator is working. Open-drain outputs of three timers No function (must be connected) Open-drain outputs Outputs that can be controlled via the port for triggering an interrupt on a processor for example. 28 44 1 43 19 20 21 22 16 17 18 26 23 24 25 PD VSS VDD N.C. XTAL1 XTAL2 CLKQ WDO WD1 WD2 WD3 VSS Int1 Int2 Int3 Semiconductor Group 4 SAE 81C80 A www.DataSheet4U.com Figure 1 Principle of the Dual-Port-RAM (DPR) Semiconductor Group 5 SAE 81C80 A www.DataSheet4U.com Figure 2 Interfacing Master and Slave Processors by DPRs Semiconductor Group 6 SAE 81C80 A www.DataSheet4U.com Figure 3 Dual-Port RAM used between Measured-Data Acquisition and the Actuators Functional Description Dual-Port RAM The SAE 81C80A is a 504-byte static RAM simultaneously accessible by two microcontrollers. The memory locations are selected via a multiplexed address/data bus and two chip-select inputs. The direction of data transfer is determined by the RD and WR inputs. There will be no undefined states when a memory location is concurrently accessed by two processors, even if they write simultaneously to the same memory location. Depending on the internal state of the access control and the actual physical sequence, the value one of the two ports will be stored. Also, if one memory location is read and written to at the same time, the data will not be mixed, i.e. either the original data or the new data are read out. Semiconductor Group 7 SAE 81C80 A www.DataSheet4U.com Chip-Select Inputs The chip-select inputs affect signals WR and RD, but not the ALE input. Therefore, the ALE signal on the DPR (even if the DPR is not selected) must correspond to the specified values. To eliminate selection, it is sufficient if one of the two chip-select inputs becomes inactiv.


LTD226 SAE81C80A 2SC3591


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