Document
K7J323682M K7J321882M www.DataSheet4U.com
Document Title
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
1Mx36-bit, 2Mx18-bit DDR II SIO b2 SRAM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Pin name change from DLL to Doff 2. Update JTAG test conditions. 3. Reserved pin for high density name change from NC to Vss/SA 4. Delete AC test condition about Clock Input timing Reference Level 5. Delete clock description on page 2 and add HSTL I/O comment 6. Deleted R/W control pin description on page 2 1. Update current characteristics in DC electrical characteristics 2. Change AC timing characteristics 3. Update JTAG instruction coding and diagrams 1. Add AC electrical characteristics. 2. Change AC timing characteristics. 3. Change DC electrical characteristics(ISB1) 1. Change the data Setup/Hold time. 2. Change the Access Time.(tCHQV, tCHQX, etc.) 3. Change the Clock Cycle Time.(MAX value of tKHKH) 4. Change the JTAG instruction coding. 1. Change the Boundary scan exit order. 2. Change the AC timing characteristics(-25, -20) 3. Correct the Overshoot and Undershoot timing diagrams. 1. Change the JTAG Block diagram 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) 1. Change the Maximum Clock cycle time. 2. Correct the 165FBGA package ball size. 1. Final spec release 1. Delete the x8 Org. part 1. Change the operating current parameter before after Isb1 -25 : 230 250 -20 : 200 230 -16 : 190 220 Draft Date July, 15 2001 Dec, 14 2001 Remark Advance Preliminary
0.2
July, 29. 2002
Preliminary
0.3
Sep. 6. 2002
Preliminary
0.4
Oct. 7. 2002
Preliminary
0.5
Dec. 16, 2002
Preliminary
0.6 0.7
Dec. 26, 2002 Mar. 20, 2003
Preliminary Preliminary
0.8
April. 4, 2003
Preliminary
1.0 2.0 2.1
Oct. 31, 2003 Dec. 1, 2003 Dec. 13, 2004
Final Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Dec. 2004 Rev 2.1
K7J323682M K7J321882M www.DataSheet4U.com
1Mx36 & 2Mx18 DDR II SIO b2 SRAM
1Mx36-bit, 2Mx18-bit DDR II SIO b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide output data valid window and future freguency scaling. • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O. • Separate independent read and write data ports • HSTL I/O • Synchronous pipeline read with self timed late write. • Registered address, control and data input/output. • Full data coherency, providing most current data. • DDR(Double Data Rate) Interface on read and write ports. • Fixed 2-bit burst for both read and write operation. • Clock-stop supports to reduce current. • Two input clocks(K and K) for accurate DDR timing at clock.