IDT70V37L

www.DataSheet4U.com HIGH-SPEED 3.3V 32K x 18 DUAL-PORT STATIC RAM PRELIMINARY IDT70V37L x .eatures True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) Low-power operation – IDT70V37L Active: 440mW (typ.) Standby: 660µW (typ.) Dual chip enables allow for depth expansion without external logic IDT70V37 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device x x x x x x x x x x x x x M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL-compatible, single 3.3V (±0.3V) power supply Available in a 100-pin TQFP Industrial temperature range (–40°C to +85°C) is available for selected speeds .unctional Block Diagram R/WL UBL CE0L CE1L OEL LBL R/WR UBR CE0R CE1R OER LBR I/O 9-17L I/O 0-8L BUSYL (1,2) A14L A0L 32Kx18 MEMORY ARRAY 70V37 15 15 I/O9-17R I/O Control I/O Control I/O0-8R BUSYR A14R A0R (1,2) . Address Decoder Address Decoder CE0L CE1L OEL R/WL SEML ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0R CE1R OER R/WR SEMR (2) INTR 4851 drw 01 M/S NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it ...