ADEBC2808

A-Data www.DataSheet4U.com ADEBC2808 PC-133 SDRAM Unbuffered SO-DIMM 32Mx64bits SDRAM DIMM based on 16Mx16, 4Bank, 8K Refresh, 3.3V SDRAM General Description The ADEBC2808 is 32Mx64 bits Synchronous DRAM Modules, The modules are composed of eight 16Mx16 bits CMOS Synchronous DRAMs in TSOP-II 400mil 54pin package and one 2Kbit EEPROM in 8pin TSSOP(TSOP) package on a 144pin glass–epoxy printed circuit board. The A-Data is a Dual In-line Memory Module and is intended for mounting onto 144-pins edge connector sockets. Fully synchronous operation referenced to the positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock. The data paths are internally pipelined to achieve very high bandwidth. Features PC-133 support Auto refresh and self refresh 8192 refresh cycles / 64ms Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface Data mask function by DQM Serial Presence Detect with EEPROM Module bank : two physical bank PCB : BSS960,Height (31.75mm),double sided component, Six layers Ordering Information. Part No. ADEBC2808 Frequency 133Mhz Bank 4 Banks Ref. 8K Package TSOP II Pin Assignment FRONT SIDE BACK SIDE PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME 1 VSS 19 DQ7 37 DQ8 55 VSS 73 NC 91 VSS 109 A9 127 DQ27 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 VDD VDD DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 20 21 DQ39 VSS 38 39 DQ40 DQ9 DQ41 DQ10 DQ42 DQ...