(K7N401801A / K7N403601A) 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
K7N403601A K7N401801A
www.DataSheet4U.com
128Kx36 & 256Kx18 Pipelined NtRAMTM
Document Title
128Kx36 & 256Kx18-Bit Pip...
Description
K7N403601A K7N401801A
www.DataSheet4U.com
128Kx36 & 256Kx18 Pipelined NtRAMTM
Document Title
128Kx36 & 256Kx18-Bit Pipelined NtRAM TM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Changed DC condition at Icc and ISB. Icc ; from 350mA to 400mA at -16, from 340mA to 390mA at -15, from 310mA to 360mA at -13, ISB ; from 130mA to 140mA at -16, from 120mA to 130mA at -15, from 120mA to 130mA at -13, 1.0 1. Final spec release 2. Changed input & output capacitance. CIN ; from 6pF to 5pF, COUT ; from 8pF to 7pF, May. 15. 2000 Final Draft Date Jan. 20. 2000 April. 03. 2000 Remark Preliminary Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
May 2000 Rev 1.0
K7N403601A K7N401801A
www.DataSheet4U.com
128Kx36 & 256Kx18 Pipelined NtRAMTM
128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
GENERAL DESCRIPTION
The K7N403601A and K7N401801A are 4,718,592 bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order contr...
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