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IDT72V3631 Dataheets PDF



Part Number IDT72V3631
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description CMOS FIFO
Datasheet IDT72V3631 DatasheetIDT72V3631 Datasheet (PDF)

www.DataSheet4U.com 3.3 VOLT CMOS SyncFIFOTM 512 x 36 1,024 x 36 2,048 x 36 • • • • IDT72V3631 IDT72V3641 IDT72V3651 FEATURES • • • • • • • • • • • Storage capacity: IDT72V3631 - 512 x 36 IDT72V3641 - 1,024 x 36 IDT72V3651 - 2,048 x 36 Supports clock frequencies up to 67 MHz Fast access times of 10ns Free-running CLKA and CLKB can be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) Clocked FIFO buffering data from Port A to Port B Synchro.

  IDT72V3631   IDT72V3631


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www.DataSheet4U.com 3.3 VOLT CMOS SyncFIFOTM 512 x 36 1,024 x 36 2,048 x 36 • • • • IDT72V3631 IDT72V3641 IDT72V3651 FEATURES • • • • • • • • • • • Storage capacity: IDT72V3631 - 512 x 36 IDT72V3641 - 1,024 x 36 IDT72V3651 - 2,048 x 36 Supports clock frequencies up to 67 MHz Fast access times of 10ns Free-running CLKA and CLKB can be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) Clocked FIFO buffering data from Port A to Port B Synchronous read retransmit capability Mailbox register in each direction Programmable Almost-Full and Almost-Empty flags Microprocessor interface control logic Input Ready (IR) and Almost-Full (AF) flags synchronized by CLKA Output Ready (OR) and Almost-Empty (AE) flags synchronized by CLKB Available in 132-pin plastic quad flat package (PQFP) or spacesaving 120-pin thin quad flat package (TQFP) Pin and functionally compatible versions of the 5V operating IDT723631/723641/723651 Easily expandable in width and depth Industrial temperature range (–40°C to +85°C) is available DESCRIPTION The IDT72V3631/72V3641/72V3651 are pin and functionally compatible versons of the IDT723631/723641/723651, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic highspeed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. The 512/1,024/2,048 x 36 dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO operates in First Word Fall Through mode and has flags to indicate empty and full conditions and conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. Communication between each port may take place with FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register Input Register RAM ARRAY 512 x 36 1,024 x 36 2,048 x 36 Sync Retransmit Logic RST Reset Logic Output Register CLKA CSA W/RA ENA MBA Port-A Control Logic RTM RFM B0 - B35 OR AE 36 A0 - A35 IR AF Write Pointer Read Pointer Status Flag Logic FS0/SD FS1/SEN 10 Flag Offset Registers Port-B Control Logic CLKB CSB W/RB ENB MBB 4658 drw 01 Mail 2 Register MBF2 IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1 1  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2003 DSC-4658/1 IDT72V3631/72V3641/72V3651 3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36 COMMERCIAL TEMPERATURE RANGE DESCRIPTION (CONTINUED) two 36-bit mailbox registers. Each mailbox register has a flag to signal when www.DataSheet4U.com new mail has been stored. Two or more devices may be used in parallel to create wider data paths. Expansion is also possible in word depth. These devices are a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOWto-HIGH transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are two-stage synchronized to CLKA. The Output Ready (OR) flag and Almost-Empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be programmed from port A or through a serial input. The IDT72V3631/72V3641/72V3651 are characterized for operation from 0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by special order. These devices are fabricated using IDT's high speed, submicron CMOS technology. PIN CONFIGURATION NC NC VCC CLKB ENB W/RB CSB GND MBF1 GND MBB NC VCC RFM RTM FS1/SEN FS0/SD GND RST MBA MBF2 VCC AE AF VCC OR IR CSA W/RA ENA CLKA GND NC NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 * NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VC.


SBG1045 IDT72V3631 IDT72V3641


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