Platform Flash In-System Programmable Configuration PROMS
R
4 2
Platform Flash In-System Programmable Configuration PROMS
Preliminary Product Specification
DS123 (v2.6) March ...
Description
R
4 2
Platform Flash In-System Programmable Configuration PROMS
Preliminary Product Specification
DS123 (v2.6) March 14, 2005
0
Features
In-System Programmable PROMs for Configuration of Xilinx FPGAs Low-Power Advanced CMOS NOR FLASH Process Endurance of 20,000 Program/Erase Cycles Operation over Full Industrial Temperature Range (–40°C to +85°C) IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing JTAG Command Initiation of Standard FPGA Configuration Cascadable for Storing Longer or Multiple Bitstreams Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ) I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V Design Support Using the Xilinx Alliance ISE and Foundation ISE Series Software Packages XCF01S/XCF02S/XCF04S - 3.3V supply voltage - Serial FPGA configuration interface (up to 33 MHz) - Available in small-footprint VO20 and VOG20 packages. XCF08P/XCF16P/XCF32P - 1.8V supply voltage - Serial or parallel FPGA configuration interface (up to 33 MHz) - Available in small-footprint VO48, VOG48, FS48, and FSG48 packages - Design revision technology enables storing and accessing multiple design revisions for configuration - Built-in data decompressor compatible with Xilinx advanced compression technology
Table 1: Platform Flash PROM Features
Density VCCINT VCCO Range VCCJ Range Packages JTAG ISP Programming Serial Parallel Config. Config. Design Revisioning Compression
XCF01S XCF02S XCF04S ...
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