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TC55V16256JI-15 Dataheets PDF



Part Number TC55V16256JI-15
Manufacturers Toshiba Semiconductor
Logo Toshiba Semiconductor
Description MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Datasheet TC55V16256JI-15 DatasheetTC55V16256JI-15 Datasheet (PDF)

TC55V16256JI/FTI-12,-15 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION The TC55V16256JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fa.

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TC55V16256JI/FTI-12,-15 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION The TC55V16256JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide lower and upper byte access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible. The TC55V16256JI/FTI is available in plastic 44-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. The TC55V16256JI/FTI guarantees −40° to 85°C operating temperature so it is suitable for use in wide operating temperature system. www.DataSheet4U.com FEATURES • Fast access time (the following are maximum values) TC55V16256JI/FTI-12:12 ns TC55V16256JI/FTI-15:15 ns Low-power dissipation (the following are maximum values) Cycle Time Operation (max) 12 230 15 200 20 170 25 150 ns mA • • • • • • • Standby:10 mA (both devices) Single power supply voltage of 3.3 V ± 0.3 V Fully static operation All inputs and outputs are LVTTL compatible Output buffer control using OE Data byte control using LB (I/O1 to I/O8) and UB (I/O9 to I/O16) Package: SOJ44-P-400-1.27 (JI) (Weight: 1.64 g typ) TSOP II44-P-400-0.80 (FTI) (Weight: 0.45 g typ) PIN ASSIGNMENT (TOP VIEW) 44 PIN SOJ 44 PIN TSOP PIN NAMES A0 to A17 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VDD GND I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VDD I/O12 I/O11 I/O10 I/O9 NU A8 A9 A10 A11 A17 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VDD GND I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VDD I/O12 I/O11 I/O10 I/O9 NU A8 A9 A10 A11 A17 I/O1 to I/O16 CE Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Data Byte Control Inputs Power (+3.3 V) Ground Not Usable (Input) WE OE LB , UB VDD GND NU (TC55V16256JI) (TC55V16256FTI) 2002-01-07 1/11 TC55V16256JI/FTI-12,-15 BLOCK DIAGRAM www.DataSheet4U.com A0 A1 A4 A5 A8 A9 A13 A14 A15 A17 ROW ADDRESS BUFFER ROW DECODER MEMORY CELL ARRAY 1,024 × 256 × 16 (4,194,304) VDD GND I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 SENSE AMP DATA OUTPUT BUFFER CE COLUMN ADDRESS BUFFER CLOCK GENERATOR A2 A3 A6 A7 A10 A11 A12 A16 VALUE −0.5 to 4.6 −0.5* to 4.6 −0.5* to VDD + 0.5** 1.4 260 −65 to 150 −40 to 100 DATA INPUT BUFFER COLUMN DECODER WE OE UB LB CE CE MAXIMUM RATINGS SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Terminal Voltage Input/Output Terminal Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING UNIT V V V W °C °C °C *: −1.5 V with a pulse width of 20% tRC min (4 ns max) **: VDD + 1.5 V with a pulse width of 20% tRC min (4 ns max) 2002-01-07 DATA OUTPUT BUFFER DATA INPUT BUFFER CE 2/11 TC55V16256JI/FTI-12,-15 DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C) www.DataSheet4U.com SYMBOL PARAMETER MIN 3.0 2.0 −0.3* TYP 3.3   MAX 3.6 VDD + 0.3** 0.8 UNIT V V V VDD VIH VIL Power Supply Voltage Input High Voltage Input Low Voltage *: −1.0 V with a pulse width of 20% tRC min (4 ns max) **: VDD + 1.0 V with a pulse width of 20% tRC min (4 ns max) DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 3.3 V ± 0.3 V) SYMBOL IIL ILO PARAMETER Input Leakage Current VIN = 0 to VDD (Except NU pin) Output Leakage Current Input Current (NU pin) Output High Voltage CE = VIH or WE = VIL or OE = VIH, VOUT = 0 to VDD TEST CONDITION MIN −1 −1 −1 −1 2.4 VDD − 0.2   tcycle = 12 ns tcycle = 15 ns tcycle = 20 ns tcycle = 25 ns       TYP               MAX 1 UNIT µA µA µA 1 20 1   0.4 0.2 230 200 170 150 55 II (NU) VIN = 0 to 0.8 V VIN = 0 to 0.2 V IOH = −2 mA IOH = −100 µA IOL = 2 mA IOL = 100 µA CE = VIL, IOUT = 0 mA, VOH V VOL Output Low Voltage IDDO Operating Current OE = VIH, mA Other Input = VIH/VIL IDDS1 IDDS2 CE = VIH, Other Input = VIH or VIL Standby Current CE = VDD − 0.2 V, Other Input = VDD − 0.2 V or 0.2 V mA 10 CAPACITANCE (Ta = 25°C, f = 1 .0 MHz) SYMBOL CIN CI/O Note: PARAMETER Input Capacitance Input/Output Capacitance VIN = GND VI/O = GND TEST CONDITION MAX 6 8 UNIT pF pF This parameter is periodically sampled and is not 100% tested. 2002-01-07 3/11 TC55V16256JI/FTI-12,-15 OPERATING MODE www.DataSheet4U.com.


TC55V16256JI-12 TC55V16256JI-15 LA317


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