Document
TEL Original Products
TE7753/TE7754 DATA SHEET
TE7753/TE7754
SUPER I/O EXPANDER
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[Outline] TE7753 and TE7754 are peripheral devices connected to a microprocessor, or general-purpose interface devices each having nine 8-bit parallel data input/output ports. Two port I/O setting modes, soft mode and hard mode, can be selected. Switching the modes eases the connection to an 86-series or 68-series CPU. [Characteristics] 1. 2. 3. 4. 5. Equipped with nine 8-bit parallel I/O ports Allowing I/O setting in bit units (port 8 only) Interface designed for connections with various types of CPUs High drive current (IOL = 12 mA: Port 9 only) Choice of two modes Soft mode : I/O setting is enabled for nine ports by software instructions from the CPU. Hard mode : I/O setting is enabled for six ports by hardware setting of pins IOS2 to IOS0. 6. Space merit (body size 14 mm x 14 mm) 7. State of ports after resetting Soft mode : All ports are in input state. Hard mode : TE7753: Output ports are in High state. TE7754: Output ports are in Low state. 8. CMOS, 5 V (single supply voltage)
Rev.1.00
TOKYO ELECTRON DEVICE LIMITED
1
TEL Original Products
[Contents]
TE7753/TE7754
[Outline] ..................................................................................................................................................1 [Characteristics].......................................................................................................................................1 [Contents] ...............................................................................................................................................2 [Block Diagram] .......................................................................................................................................3 [Pin Assignments] ....................................................................................................................................4 [Description of Pins] .................................................................................................................................5 [CPU Interface] ........................................................................................................................................7 [Description of Operation] .........................................................................................................................8 www.DataSheet4U.com 1. Soft mode and hard mode ................................................................................................................8 2. Setting each port for input or output using CR .................................................................................. 12 [Absolute maximum ratings].................................................................................................................... 13 [Recommended operation conditions] ..................................................................................................... 13 [DC characteristics]................................................................................................................................ 14 [Input/output pin capacity]....................................................................................................................... 14 [AC characteristics]................................................................................................................................ 15 [Reset input conditions] .......................................................................................................................... 22 [Outside dimensions].............................................................................................................................. 23 [Notations] 1. Voltage levels are indicated differently for input and output signals. Voltage level VDD VSS Input signal 1 0 Output signal H L
2. A signal with the enable level being negative logic is indicated with its name preceded by # as shown below: Examples: #CS, #RD 3. The value indicated in a register is the initial value after resetting.
Rev.1.00
TOKYO ELECTRON DEVICE LIMITED
2
TEL Original Products
[Block Diagram]
TE7753/TE7754
CR0
8
I/O Port 1
P17 ~ 10
8 D7 ~ 0
Data Bus Buffer
4 P23 ~ 20
I/O Port 2 CR1
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4
P27 ~ 24
A3 A2 A1 A0
8
Adress Decoder I/O Port 3
P37 ~ 30
8 8 #RESET #CS #RD/R#W #WR/#MEN
Control Logic I/O Port 4
P47 ~ 40
4 P53 ~ 50
CR2 I/O Port 5
4 P57 ~ 54 IOS2 IOS1 IOS0
I/O Port 6
8 P67 ~ 60
MS
Mode Selector
8
I/O Port 7
P77 ~ 70
8
P80 P81 P82 P83 P84 P85 P86 P87
CR3
I/O Port 8
8
I/O Port 9
P97 ~ 90
Rev.1.00
TOKYO ELECTRON DEVICE LIMITED
3
TEL Original Products
[Pin Assignments] NO. I/O SYMBOL 1 VDD 2 B P81 3 B P82 4 B P83 5 B P84 6 B P85 7 B P86 8 B P87 9 B P90 10 B P91 www.DataSheet4U.com 11 B P92 12 B P93 13 B P94 14 B P95 15 B P96 16 B P97 17 B P10 18 B P11 19 B P12 20 B P13 21 B P14 22 B P15 23 B P16 24 B P17 25 VDD 26 VSS 27 B P20 28 B P21.