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ICS83948I-01 Dataheets PDF



Part Number ICS83948I-01
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Datasheet ICS83948I-01 DatasheetICS83948I-01 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS83948I-01 LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER FEATURES • 12 LVCMOS outputs • Selectable LVCMOS clock or differential CLK, nCLK inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 150MHz • Output skew: 350ps (maximum) • Part to part skew: 1.5ns (maximum) • 3.3V core, 3.3V output • -40°C to 85°C.

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Integrated Circuit Systems, Inc. ICS83948I-01 LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER FEATURES • 12 LVCMOS outputs • Selectable LVCMOS clock or differential CLK, nCLK inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 150MHz • Output skew: 350ps (maximum) • Part to part skew: 1.5ns (maximum) • 3.3V core, 3.3V output • -40°C to 85°C ambient operating temperature • Pin compatible with the MPC948/948L GENERAL DESCRIPTION The ICS83948I-01 is a low skew, 1-to-12 Differential-to-LVCMOS Fanout Buffer and a member HiPerClockS™ of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS83948I-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50 Ω series or parallel terminated transmission lines. The www.DataSheet4U.com effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. ,&6 The ICS83948I-01 is characterized at 3.3V core/3.3V output. Guaranteed output and part-to-part skew characteristics make the ICS83948I-01 ideal for those clock distribution applications demanding well defined performance and repeatability. BLOCK DIAGRAM CLK_EN D Q LVCMOS_CLK CLK nCLK 1 Q0 0 Q1 CLK_SEL Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 OE PIN ASSIGNMENT GND GND VDDO VDDO Q0 Q1 Q2 Q3 32 31 30 29 28 27 26 25 CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Q11 VDDO Q10 GND Q9 VDDO Q8 GND 24 23 22 GND Q4 VDDO Q5 GND Q6 VDDO Q7 ICS83948I-01 21 20 19 18 17 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 83948AYI-01 www.icst.com/products/hiperclocks.html 1 REV. A SEPTEMBER 23, 2002 Integrated Circuit Systems, Inc. ICS83948I-01 LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER Name CLK_SEL Input Input Input Input Input Input Power Power Output Power Type Pullup Pullup Pullup Pullup Pullup Description Clock select input. Selects LVCMOS clock input when HIGH. Selects CLK, nCLK inputs when LOW. LVCMOS / LVTTL interface levels. Clock input. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Clock enable. LVCMOS / LVTTL interface levels. Output enable. LVCMOS / LVTTL interface levels. Core supply pin. Power supply ground. Clock outputs. LVCMOS / LVTTL interface levels. Output supply pins. TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 www.DataSheet4U.com LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 VDDO Pulldown Inver ting differential clock input. 5 6 7 8, 12, 16, 20, 24, 28, 32 9, 11, 13, 15, 17, 19, 21, 23 25, 27, 29, 31 10, 14, 18, 22, 26, 30 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance Test Conditions Minimum Typical Maximum 4 25 51 51 7 Units pF pF KΩ KΩ Ω TABLE 3A. CLOCK SELECT FUNCTION TABLE Control Input CLK_SEL 0 1 CLK, nCLK Selected De-selected Clock LVCMOS_CLK De-selected Selected TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK_SEL 0 0 0 0 0 0 1 1 LVCMOS_CLK — — — — — — 0 1 CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 — — nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 — — Outputs Q0:Q12 LOW HIGH LOW HIGH HIGH LOW LOW HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting Non Inver ting Non Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 83948AYI-01 www.icst.com/products/hiperclocks.html 2 REV. A SEPTEMBER 23, 2002 Integrated Circuit Systems, Inc. ICS83948I-01 LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, Tstg Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the www.DataSheet4U.com DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY .


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