ICS8344-01

Integrated Circuit Systems, Inc. ICS8344-01 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER FEATURES 24 LVCMOS outputs, 7Ω typical output impedance 2 selectable CLKx, nCLKx inputs CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Output frequency up to 250MHz Translates any single ended input signal to LVCMOS with resistor bias on nCLK input Synchronous clock enable Output skew: 200 ps (maximum) Part-to-part skew: 900ps (maximum) Bank skew: 85ps (maximum) Propagation delay: 5ns (maximum) 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes 0°C to 70°C ambient operating temperature Industrial temperature information available upon request GENERAL DESCRIPTION The ICS8344-01 is a low voltage, low skew fanout buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8344-01 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The ICS8344-01 is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated www.DataSheet4U.com transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate boar...