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ICS83021I Dataheets PDF



Part Number ICS83021I
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Datasheet ICS83021I DatasheetICS83021I Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR FEATURES • One LVCMOS / LVTTL output • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 350MHz (typical) • Part-to-part skew: 500ps (maximum) • Additive phase jitter, RMS: 0.21ps (typical), 3.3V output • Small 8 lead SOIC package saves board space • Full 3.3V, 2.5V operating supply .

  ICS83021I   ICS83021I



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Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR FEATURES • One LVCMOS / LVTTL output • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 350MHz (typical) • Part-to-part skew: 500ps (maximum) • Additive phase jitter, RMS: 0.21ps (typical), 3.3V output • Small 8 lead SOIC package saves board space • Full 3.3V, 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages GENERAL DESCRIPTION T h e I C S 8 3 021I i s a 1 - t o -1 Differential-toLVCMOS/LVTTL Translator and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The differential input is highly flexible and can accept the following input types: LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space. IC S www.DataSheet4U.com BLOCK DIAGRAM CLK nCLK Q0 PIN ASSIGNMENT nc CLK nCLK nc 1 2 3 4 8 7 6 5 VDD Q0 nc GND ICS83021I 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 83021AMI www.icst.com/products/hiperclocks.html 1 REV. C DECEMBER 12, 2005 Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Type Unused Input Input Power Output Power Pullup Description No connect. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Power supply ground. Single clock output. LVCMOS / LVTTL interface levels. Positive supply pin. TABLE 1. PIN DESCRIPTIONS Number 1, 4, 6 2 3 5 7 www.DataSheet4U.com 8 Name nc CLK nCLK GN D Q0 VDD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 5 Test Conditions Minimum Typical 4 VDD = 3.6V 23 51 51 7 12 Maximum Units pF pF kΩ kΩ Ω 83021AMI www.icst.com/products/hiperclocks.html 2 REV. C DECEMBER 12, 2005 Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR 4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 112.7°C/W (0 lfpm) -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG www.DataSheet4U.com TABLE .


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