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LH53517 Dataheets PDF



Part Number LH53517
Manufacturers Sharp Electrionic Components
Logo Sharp Electrionic Components
Description CMOS 512K (64K x 8) MROM
Datasheet LH53517 DatasheetLH53517 Datasheet (PDF)

LH53517 FEATURES • 65,536 words × 8 bit organization • Access time: 150 ns (MAX.) • Low-power consumption: Operating: 165 mW (MAX.) Standby: 550 µW (MAX.) • Static operation • TTL compatible I/O • Three-state outputs • Single +5 V power supply • Mask-programmable OE/OE • Packages: 28-pin, 600-mil DIP 28-pin, 450-mil SOP 28-pin, 8 × 13.4 mm2 TSOP (Type I) DESCRIPTION The LH53517 is a mask-programmable ROM organized as 65,536 × 8 bits. It is fabricated using silicon-gate CMOS process technology. 2.

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LH53517 FEATURES • 65,536 words × 8 bit organization • Access time: 150 ns (MAX.) • Low-power consumption: Operating: 165 mW (MAX.) Standby: 550 µW (MAX.) • Static operation • TTL compatible I/O • Three-state outputs • Single +5 V power supply • Mask-programmable OE/OE • Packages: 28-pin, 600-mil DIP 28-pin, 450-mil SOP 28-pin, 8 × 13.4 mm2 TSOP (Type I) DESCRIPTION The LH53517 is a mask-programmable ROM organized as 65,536 × 8 bits. It is fabricated using silicon-gate CMOS process technology. 28-PIN DIP 28-PIN SOP CMOS 512K (64K × 8) MROM PIN CONNECTIONS TOP VIEW A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A14 A13 A8 A9 A11 OE/OE A10 CE D7 D6 D5 D4 D3 53517-1 Figure 1. Pin Connections for DIP and SOP Packages 28-PIN TSOP (Type I) TOP VIEW OE/OE A11 A9 A8 A13 A14 VCC A15 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE D7 D6 D5 D4 D3 GND D2 D1 D0 A0 A1 A2 NOTE: Reverse bend available on request. 53517-2 Figure 2. Pin Connections for TSOP Package 1 LH53517 CMOS 512K MROM A8 25 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 ADDRESS DECODER ADDRESS BUFFER A15 1 A14 27 A13 26 A12 2 A11 23 A10 21 A9 24 MEMORY MATRIX (65,536 x 8) COLUMN SELECTOR SENSE AMPLIFIER CE 20 CE BUFFER TIMING GENERATOR DATA OUTPUT BUFFER OE/OE 22 OE BUFFER 28 14 VCC GND NOTE: Pin numbers apply to the 28-pin DIP or SOP. 19 D7 18 D6 17 D5 16 D4 15 D3 13 D2 12 D1 11 D0 53517-3 Figure 3. LH53517 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE A0 – A15 D0 – D7 CE Address input Data output Chip enable input OE/OE VCC GND Output enable input Power supply (+5 V) Ground 1 NOTE: 1. Active level of OE/OE is mask-programmable. TRUTH TABLE CE OE/OE DATA OUTPUT CURRENT CONSUMPTION H L NOTE: X = H or L X L/H H/L High-Z Output Standby Operating ABSOLUTE MAXIMUM RATINGS 2 CMOS 512K MROM LH53517 PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature Storage temperature VCC VIN VOUT Topr Tstg –0.3 to +7.0 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 0 to +70 –65 to +150 V V V °C °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input ‘Low’ voltage Input ‘High’ voltage Output ‘Low’ voltage Output ‘High’ voltage Input leakage current Output leakage current VIL VIH VOL VOH | ILI | | ILO | ICC1 ICC2 ICC3 ICC4 ISB1 ISB2 CIN COUT I OL = 1.6 mA I OH = –400 µA V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 150 ns t RC = 1 µ s t RC = 150 ns t RC = 1 µ s CE = V IH CE = V CC – 0.2 V f = 1 MHz T A = 25° C –0.3 2.2 2.4 0.8 VCC + 0.3 0.4 10 10 30 15 25 12 2 100 10 10 V V V V µA µA mA mA mA µA pF pF 1 2 3 Operating current Standby current Input capacitance Output capacitance NOTES: 1. CE/OE = VIH , OE = VIL 2. VIN = VIH/VIL, CE = VIL, outputs open 3. VIN = (VCC – 0.2 V), 0.2 V, CE = 0.2 V, outputs open AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70 °C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z tRC tAA tACE tOE tOH tCHZ tOHZ 150 150 150 10 5 70 70 80 ns ns ns ns ns ns ns 1 1 NOTE: 1. This is the time required for the output to become high-impedance. 3 LH53517 CMOS 512K MROM AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input rise/fall time Input reference level Output reference level Output load condition 0.6 V to 2.4 V 10 ns 1.5 V 0.8 V and 2.2 V 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the V CC pin and the GND pin. tRC A0 - A15 tAA (NOTE) CE tACE (NOTE) OE OE tOE (NOTE) tOHZ tCHZ D0 - D7 DATA VALID tOH NOTE: Data becomes valid after the intervals tAA, tACE, and tOE from address input, chip enable, and output enable, respectively have been met. 53517-4 Figure 4. Timing Diagram 4 CMOS 512K MROM LH53517 PACKAGE DIAGRAMS 28DIP (DIP028-P-0600) 28 15 DETAIL 13.45 [0.530] 12.95 [0.510] 1 36.30 [1.429] 35.70 [1.406] 14 0° TO 15° 0.30 [0.012] 0.20 [0.008] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 0.51 [0.020] MIN. DIMENSIONS IN MM [INCHES] 28DIP-2 28-pin, 600-mil DIP 28SOP (SOP028-P-0450) 1.27 [0.050] TYP. 1.70 [0.067] 15 8.80 [0.346] 8.40 [0.331] 12.40 [0.488] 11.60 [0.457] 0.50 [0.020] 0.30 [0.012] 28 10.60 [0.417] 1 18.20 [0.717] 17.80 [0.701] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 2.


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