CMOS 64K x 18 Static RAM
LH521028
FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word (18-Bits) for: – Improved Performance – Reduced Compon...
Description
LH521028
FEATURES Fast Access Times: 17/20/25/35 ns Wide Word (18-Bits) for: – Improved Performance – Reduced Component Count – Nine-bit Byte for Parity Transparent Address Latch Reduced Loading on Address Bus Low-Power Stand-by Mode when Deselected TTL Compatible I/O 5 V ± 10% Supply 2 V Data Retention JEDEC Standard Pinout Package: 52-Pin PLCC
52-PIN PLCC
CMOS 64K × 18 Static RAM
operations on the high and the low bytes. The Address Latches are transparent when ALE is HIGH (for applications not requiring a latch), and are latched when ALE is LOW. The Address Latches and the wide word help to eliminate the need for external Address busbuffers and/or latches. Write cycles occur when Chip Enable (E), SH and/or SL, and Write Enable (W) are LOW. The Byte-select signals can be used for Byte-write operations by disabling the other byte during the Write operation. Data is transferred from the DQ pins to the memory location specified by the 16 address lines. The proper use of the Output Enable control (G) can prevent bus contention. When E and either SH or SL are LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address with ALE HIGH.
PIN CONNECTIONS
TOP VIEW
ALE VCC VSS A15 A14 A0 SL A13
46 45 44 43 42 41 40 39 38 37 36 35 34 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS V...
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