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MPC948L Dataheets PDF



Part Number MPC948L
Manufacturers Motorola
Logo Motorola
Description LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP
Datasheet MPC948L DatasheetMPC948L Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information Low Voltage 1:12 Clock Distribution Chip The MPC948L is a 1:12 low voltage clock distribution chip. The device is pin and function compatible with the MPC948 with the added feature of 2.5V output capabilities. The device features the capability to select either a differential LVPECL or a LVTTL compatible input. The 12 outputs are 2.5V LVCMOS or LVTTL compatible and feature the drive strength to drive 50Ω series terminated transmission l.

  MPC948L   MPC948L


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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information Low Voltage 1:12 Clock Distribution Chip The MPC948L is a 1:12 low voltage clock distribution chip. The device is pin and function compatible with the MPC948 with the added feature of 2.5V output capabilities. The device features the capability to select either a differential LVPECL or a LVTTL compatible input. The 12 outputs are 2.5V LVCMOS or LVTTL compatible and feature the drive strength to drive 50Ω series terminated transmission lines. With output–to–output www.DataSheet4U.com skews of 350ps, the MPC948L is ideal as a clock distribution chip for the most demanding of synchronous systems. MPC948L LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP • • • • • • • • • Clock Distribution for Intel Microprocessors LVPECL or LVCMOS/LVTTL Clock Input 350ps Maximum Output–to–Output Skew Drives Up to 24 Independent Clock Lines Maximum Output Frequency of 150MHz Synchronous Output Enable Tristatable Outputs 32–Lead TQFP Packaging 2.5V Output Capability FA SUFFIX 32–LEAD TQFP PACKAGE CASE 873A–02 With an output impedance of approximately 7Ω, in both the HIGH and LOW logic states, the output buffers of the MPC948L are ideal for driving series terminated transmission lines. More specifically, each of the 12 MPC948L outputs can drive two series terminated 50Ω transmission lines. With this capability, the MPC948L has an effective fanout of 1:24 in applications where each line drives a single load. The differential LVPECL inputs of the MPC948L allow the device to interface directly with a LVPECL fanout buffer like the MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the TTL_CLK_Sel pin will select the TTL level clock input. All of the control inputs are LVCMOS/LVTTL compatible. The MPC948L provides a synchronous output enable control to allow for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test, the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into high impedance. Note that all of the MPC948L inputs have internal pullup resistors. The 32–lead TQFP package was chosen to optimize performance, board space and cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing. The MPC948L features two independent power supplies; VCCI and VCCO. The VCCI pin powers the internal core logic and must be tied to 3.3V. The VCCO pin powers the output buffer and can be tied to either 2.5V or 3.3V. This document contains information on a new product. Specifications and information herein are subject to change without notice. 4/97 © Motorola, Inc. 1997 1 REV 0 MPC948L VCCI PECL_CLK PECL_CLK TTL_CLK TTL_CLK_Sel Sync_OE Tristate VCCO 0 1 12 Q0–Q11 Figure 1. Logic Diagram www.DataSheet4U.com VCCO VCCO 18 GND GND Q4 Q5 Q6 Q7 17 16 15 14 13 GND Q8 VCCO Q9 Sync_OE 12 11 10 9 1 2 3 4 5 6 7 8 GND Q10 VCCO Q11 0 1 Tristate 0 1 Outputs Disabled Enabled Outputs Tristate Enabled 24 Q3 VCCO Q2 GND Q1 VCCO Q0 GND 25 26 27 28 23 22 21 20 19 FUNCTION TABLES TTL_CLK_Sel 0 1 Input PECL_CLK TTL_CLK MPC948L 29 30 31 32 PECL_CLK TTL_CLK_Sel PECL_CLK TTL_CLK Tristate VCCI Figure 2. 32–Lead Pinout (Top View) TTL_CLK Sync_OE Q Sync_OE Figure 3. Sync_OE Timing Diagram MOTOROLA GND 2 TIMING SOLUTIONS BR1333 — Rev 6 MPC948L ABSOLUTE MAXIMUM RATINGS* Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range –40 Parameter Min –0.3 –0.3 Max 4.6 VDD + 0.3 ±20 125 Unit V V mA °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. DC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 3.3V ±5%; VCCO = 2.5V ±5% or 3.3V ±5%) Symbol VIH www.DataSheet4U.com VIL VPP VCMR VOH VOL IIN CIN Cpd ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak–to–Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Maximum Quiescent Supply Current 25 22 30 PECL_CLK Other PECL_CLK Other PECL_CLK PECL_CLK VCCO = 3.3V VCCO = 2.5V Min 2.135 2.0 1.49 300 VCC – 2.0 2.5 2.0 0.4 ±100 4 Typ Max 2.42 3.60 1.825 0.8 1000 VCC – 0.6 Unit V V mV V V V µA pF pF mA Per Output Note 1. IOH = –20mA (Note 2.) IOL = 20m.


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