LH28F016SA

LH28F016SA FEATURES 16M (1M × 16, 2M × 8) Flash Memory 56-PIN TSOP TOP VIEW User-Configurable x8 or x16 Operation User-Selectable 3.3 V or 5 V VCC 70 ns Maximum Access Time 0.43 MB/sec Write Transfer Rate 100,000 Erase Cycles per Block 32 Independently Lockable Blocks (64K) Revolutionary Architecture – Pipelined Command Execution – Write During Erase – Command Superset of Sharp LH28F008SA 3/5 CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WP WE OE RY/BY DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE NC NC 50 µA (Typ.) ICC in CMOS Standby 1 µA (Typ.) Deep Power-Down State-of-the-Art 0.55 µm ETOX™ Flash Technology 56-Pin, 1.2 mm × 14 mm × 20 mm TSOP (Type I) Package 28F016SAT-1 Figure 1. TSOP Configuration 1 LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory DQ8 - DQ15 DQ0 - DQ7 OUTPUT BUFFER OUTPUT BUFFER INPUT BUFFER INPUT BUFFER ID REGISTER DATA QUEUE REGISTERS I/O LOGIC 3/5 BYTE CSR OUTPUT MULTIPLEXER PAGE BUFFERS ESRs CE0 CE1 OE CUI WE WP RP DATA COMPARATOR A0 - A20 INPUT BUFFER Y-DECODER Y GATING/SENSING 64KB BLOCK 30 64KB BLOCK 31 64KB BLOCK 0 64KB BLOCK 1 WSM RY/BY ADDRESS QUEUE LATCHES ... X-DECODER ... ADDRESS COUNTER ... PROGRAM/ ERASE VOLTAGE SWITCH VPP 3/5...