Document
DFPADD
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Floating Point Pipelined Adder Unit ver 2.50
OVERVIEW
● Fully synthesizable, static synchronous design with no internal tri-states
The DFPADD uses the pipelined mathematics algorithm to compute sum of two arguments. The input numbers format is according to IEEE-754 standard. DFPADD supports single precision real number. Add operation was pipelined up to 5 levels. Input data are fed every clock cycle. The first result appears after 5 clock periods latency and next results are available each clock cycle. Full IEEE754 precision and accuracy were included.
DELIVERABLES
♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet Synthesis scripts Example application Technical support ◊ IP Core implementation support ◊ 3 months maintenance
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APPLICATION
● ● ● ● Math coprocessors DSP algorithms Embedded arithmetic coprocessor Data processing & control ♦ ♦ ♦ ♦
KEY FEATURES
● ● ● ● ● ● ● ● ● Full IEEE-754 compliance Single precision real format support Simple interface No programming required 5 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable
Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support
LICENSING
Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows using IP Core in single FPGA bitstream and ASIC implemenhttp://www.DigitalCoreDesign.com http://www.dcd.pl
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
tation. It also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time of use limitations. ● Single Design license for
○ VHDL, Verilog source code called HDL
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BLOCK DIAGRAM
adatai(31:0) bdatai(31:0) en rst clk
Arguments Checker
Main FP Pipelined Unit
Result Composer
datao(31:0)
ofo ufo ifo
Source
○ Encrypted, or plain text EDIF called Netlist
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Unlimited Designs license for
○ HDL Source ○ Netlist
Arguments Checker - performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit. Main FP Pipelined Unit - performs floating point add function. Gives the complex .