IDT71P71604

18Mb Pipelined DDR™II SRAM Burst of 2 Features ◆ ◆ ◆ ◆ ◆ www.DataSheet4U.com ◆ ◆ ◆ ◆ IDT71P71804 IDT71P71604 Description The IDT DDRIITM Burst of two SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port. This scheme allows maximization of the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates at single data rate speeds, allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers. The DDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. Clocking The DDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the DDRII has an output “echo” clock, CQ, CQ. ◆ ◆ 18Mb Density (1Mx18, 512kx36) Common Read and Write Data Port Dual Echo Clock Output 2-Word Burst on all SRAM accesses Multiplexed Address Bus O...