29LV400BC

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20862-3E FLASH MEMORY CMOS 4M (512K × 8/256K × 16) BIT www.DataSheet4U.com MBM29LV400TC-70/-90/-12/MBM29LV400BC-70/-90/-12 s FEATURES Single 3.0 V read, program, and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 44-pin SOP (Package suffix: PF) 48-pin CSOP (Package suffix: PCV) 48-ball FBGA (Package suffix: PBT) Minimum 100,000 program/erase cycles High performance 70 ns maximum access time Sector erase architecture One 8K word, two 4K words, one 16K word, and seven 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase Boot Code Sector Architecture T = Top sector B = Bottom sector Embedded EraseTM Algorithms Automatically preprograms and erases the chip or any sector Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode Low VCC write inhibit ≤ 2....