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THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
ADVANCE INFORMATION
DS3667-1·2
SP8655A 200MHz432, SP8657A 200MHz420, SP8659B 200MHz416
The SP8655A, SP8657A and SP8659B are low power ECL counters with open collector output capable of driving TTL or CMOS and have internally biased inputs.
NC CLOCK INPUT CLOCK INPUT 7 8 NC 6 5 4 VEE (0V) OUTPUT 3 NC 1 2 VCC
FEATURES s AC Coupled Inputs
s Low Power Consumption www.DataSheet4U.com s CMOS/TTL Compatible Open Collector Output
QUICK REFERENCE DATA s Supply Voltage: 5·0V
CM8
Fig. 1 Pin connections - bottom view
s Power Consumption: 50mW s Temperature Range: 255°C to 1125°C (SP8655A,
SP8657A) 230°C to 170°C (SP8659B)
ABSOLUTE MAXIMUM RATINGS
Supply voltage Open collector output voltage Storage temperature range Max. junction temperature Max. clock input voltage Output sink current 8V 12V 265°C to 1150°C 1175°C 2·5V p-p 10mA
ORDERING INFORMATION
SP8655 A CM SP8657 A CM SP8659 B CM
2 D Q D Q D Q D Q D Q 4 OUTPUT STAGE
VCC OUTPUT
CLOCK INPUT CLOCK INPUT
1 8
D Q CK CK
D Q CK CK
D Q CK CK
D Q CK CK
D Q CK CK
SP8655A
5
VEE (0V)
2 D Q D Q REF D Q D Q D Q 4 OUTPUT STAGE
VCC OUTPUT
CLOCK INPUT CLOCK INPUT
1 8
D Q CK CK
D Q CK CK
Q CK CK
D Q CK CK
D Q CK CK
SP8657A
5
VEE (0V)
2 D Q D Q D Q D Q 4 OUTPUT STAGE
VCC OUTPUT
CLOCK INPUT CLOCK INPUT
1 8
D Q CK CK
D Q CK CK
D Q CK CK
D Q CK CK
SP8659B
5
VEE (0V)
Fig. 2 Functional diagrams
SP8655/7/9
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range Supply voltage, VCC = 5·0V± 0·25V, VEE = 0V Temperature, TAMB = 255°C to 1125°C (SP8655A, SP8657A), 230°C to 170°C (SP8659B) Value Characteristic Maximum frequency (sinewave input) Minimum frequency (sinewave input) Power supply current Output high voltage Output low voltage Symbol fMAX fMIN ICC VOH VOL Min. 200 40 13 7·5 0·45 Max. Units MHz MHz mA V V Conditions Input = 400-800mV p-p Input = 400-800mV p-p VCC = 5V, CLOAD<5pF, pin 4 = 1·5kΩ to 10V VCC = 5V, pin 4 = 1·5kΩ to 10V
NOTES 1. The test configuration for dynamic testing is shown in Fig.5. 2. Above characteristics are not tested at 25°C (tested at low and high temperatures only). www.DataSheet4U.com
1200 1000 800 600 400 200 0 0 50 100 150 INPUT FREQUENCY (MHz) 200 250
INPUT AMPLITUDE (mV p-p)
GUARANTEED * OPERATING WINDOW
* Tested as specified
in table of Electrical Characteristics
Fig. 3 Typical input characteristic
OPERATING NOTES
1.The clock inputs (pins 1 and 8) should be capacitively coupled to the signal source. When driven single ended, the input signal path is completed by a capacitor from the unused input to ground. 2. In the absence of a signal the devices will self-oscillate. This can be prevented by connecting a 39k Ω resistor from either input to ground. If the device is driven single ended, it is recommended that the pull-down resistor be connected to the decoupled unused input. There will be a loss in sensitivity of approximately 200mV. 3. The device will operate down to DC but input slew rate must be better than 100V/µs. 4. The open collector output will drive three TTL loads, and therefore requires a a suitable resistor to VCC to maintain noise immunity. In order to maintain noise immunity on transitions, this resistor should not exceed 4·7k Ω. For interfacing to CMOS, the open collector may be restored to a 110V line via a 3·3kΩ resistor. 5. Input impedance varies as a function of frequency; see Fig. 4. 6. The rise time of the open collector output waveform is directly proportional to the load capacitance and load resistor value. Therefore, the load capacitance should be minimised and the load resistor kept to a minimum compatible with system power requirements. In the test configuration of Fig. 5, the output rise time is approximately 20ns and the fall time is typically 10ns.
2
SP8655/7/9
j1 j 0.5 j2
j 0.2 j5
0
0.2
0.5
1
2
5
50 100 200
2j 5
2j 0.2
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2j 0.5 2j 1 2j 2
Fig. 4 Typical input impedance. Test conditions: supply voltage = 5·0V, ambient temperature = 25°C, frequencies in MHz, Impedances normalised to 50Ω
VCC FROM GENERATOR TO SAMPLING SCOPE 10n 1n 1 8 5 1n 7p 2 3·3k 4 1k 100n SAMPLING SCOPE INPUT 110V
DUT
Fig. 5 Test circuit
15V 1n
2 1n INPUT 1 15V/110V (DEPENDING ON CMOS SUPPLY VOLTAGE)
8
DIVIDE BY 32 (SP8655) 20 (SP8657) 16 (SP8659)
2k 2k
3·3k 4 CMOS
10k
1n
BIAS 5
Fig. 6. Typical application circuit showing interfacing
15V
2
2·2k 4
SP8655/7/9
TTL
Fig. 7. Interfacing to TTL. Load not to exceed 3 TTL unit loads
3
SP8655/7/9
PACKAGE DETAILS
Dimensions are shown thus: mm (in).
4·19/4·70 (0·165/0·185) 12·70/14·28 (0·500/0·570) 8 1 2 7 3 6 5 4 45°
4·83/5·33 P.C.D. (0·190/0·210)
8·63/9·39 8·00/8·51 (0·315/0·335) (0·340/0·370)
0·41/0·53 (0·016/0·021)
0·25/1·02 (0·010/0·040)
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NOTES 1. Controlling dimensions are inches. 2. This pa.