K4H560438D-TCB3

256Mb Key Features Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Four banks operation Differential clock inputs(CK and CK) DLL aligns DQ and DQS transition with CK transition MRS cycle with address key programs -. Read latency 2, 2.5 (clock) www.DataSheet4U.com -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) All inputs except data & DM are sampled at the positive going edge of the system clock(CK) Data I/O transactions on both edges of data strobe Edge aligned data output, center aligned data input LDM,UDM/DM for write masking only Auto & Self refresh 7.8us refresh interval(8K/64ms refresh) Maximum burst refresh cycle : 8 66pin TSOP II package DDR SDRAM ORDERING INFORMATION Part No. K4H560438D-TC/LB3 K4H560438D-TC/LA2 K4H560438D-TC/LB0 K4H560438D-TC/LA0 K4H560838D-TC/LB3 K4H560838D-TC/LA2 K4H560838D-TC/LB0 K4H560838D-TC/LA0 K4H561638D-TC/LB3 K4H561638D-TC/LA2 K4H561638D-TC/LB0 K4H561638D-TC/LA0 16M x 16 32M x 8 64M x 4 Org. Max Freq. B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0(DDR200@CL=2) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0(DDR200@CL=2) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0(DDR200@CL=2) SSTL2 66pin TSOP II SSTL2 66pin TSOP II SSTL2 66pin TSOP II Interface Package Operating Frequencies - B3(DDR333) Speed @CL2 Speed @CL2.5 133MHz 166MHz - A2(DDR266A) 133MHz 133MHz - B0(DDR266B) 100MHz 133MHz - A0(DDR200) 100MHz - *CL : Cas Latency ...