MPC954

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC954/D Low Voltage PLL Clock Driver The MPC954 is a 3.3V compatible, PLL based zero delay buffer targeted for high performance clock tree designs. With 11 outputs at frequencies of up to 100MHz and output skews of 200ps the MPC954 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle–to–cycle and phase jitter. MPC954 Fully Integrated PLL www.DataSheet4U.com Output Frequency up to 100MHz LOW VOLTAGE PLL ZERO DELAY BUFFER Outputs Disable in High Impedance TSSOP Packaging 50ps Cycle–to–Cycle Jitter Typical The analog VCC pin of the device also serves as a PLL bypass select pin. When driven low the VCCA pin will route the REF_CLK input around the PLL directly to the outputs. The OE input is a logic enable for all of the outputs except QFB. A low on the OE pin forces Q0–Q9 to a logic low state. The MPC954 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the ability to drive terminated 50Ω transmission lines. The output impedance of the MPC954 is  10W , therefore for series terminated 50Ω lines, each of the MPC954 outputs can drive two traces giving the device an effective fanout of 1:22. The device is packaged in a 24–lead TSSOP package to provide the optimum combination of board density and performance. DT SUFFIX ...