MPC952

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC952 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree applications. The device features a fully integrated PLL with no external components required. With output frequencies of up to 180MHz and eleven low skew outputs the MPC952 is well suited for high performance designs. The device employs a fully differential PLL design to optimize jitter and noise rejection performance. Jitter is an increasingly important parameter as more microprocessors and ASiC’s are employing on chip PLL clock distribution. www.DataSheet4U.com MPC952 LOW VOLTAGE PLL CLOCK DRIVER Fully Integrated PLL Output Frequency up to 180MHz High Impedance Disabled Outputs Compatible with PowerPC™, Intel and High Performance RISC Microprocessors Output Frequency Configurable TQFP Packaging ±100ps Cycle–to–Cycle Jitter The MPC952 features three banks of individually configurable outputs. The banks contain 5 outputs, 4 outputs and 2 outputs. The internal divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1. The output frequency relationship is controlled by the fsel frequency control pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL compatible inputs. FA SUFFIX TQFP PACKAGE CASE 873A-02 The MPC952 uses external feedback to the PLL. This features allows for the use of the device as a “zero delay” buffer. Any of the eleven outputs can be used...